US5291050A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS device having reduced gate-to-drain capacitance
Assignee: Fuji Electric Co Ltd
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Filing: 1991-10-22
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Granted: 1994-03-01
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Expires: 2011-10-22
Abstract
Abstract A metal-oxide-semiconductor (MOS) device designed to achieve reduced gate-to-drain capacitance is disclosed. The device has gate-electrode layer consisting of alternating polarity regions, such that regions of the gate-electrode layer not involved in channel operations have a conductivity type different from the conductivity type of the gate-electrode-layer regions actually involved in channel operations. Since the alternating conductivity regions form a capacitance in series to the gate-to-drain capacitance, the gate-to-drain capacitance of the device is reduced. An embodiment of the invention also incorporates increased-thickness regions of the gate-oxide film, which regions are disposed over semiconductor areas at which no channel operation occurs.
Inventors
- 👤 Takeyoshi Nishimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:30
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/671; H10D12/00; H10D12/411; H10D12/441
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
146 words
A metal-oxide-semiconductor device comprising: a first semiconductor region of a first conductive type having a first surface and a second surface; a plurality of second regions of a second conductive type at said first surface of said first semiconductor region; a third region of said first conductive type in each of said second regions; whereby a plurality of channel regions are formed between said third region and said first surface of said first semiconductor region; and a gate-electrode layer disposed on an insulation film over said channel regions and said first surface of said first semiconductor region; wherein said gate-electrode layer comprises first and second portions of opposite conductivity type, each one of the first portions extending across a first surface portion of said first semiconductor region, between a first region over a first channel region and a second region over a neighboring second channel region.
Claim 2
Dependent Claim
146 words
A metal-oxide-semiconductor device comprising: a first semiconductor region of a first conductive type having a first surface and a second surface; a plurality of second regions of a second conductive type at said first surface of said first semiconductor region; a third region of said first conductive type in each of said second regions; whereby a plurality of channel regions are formed between said third region and said first surface of said first semiconductor region; and a gate-electrode layer disposed on an insulation film over said channel regions and said first surface of said first semiconductor region; wherein said gate-electrode layer comprises first and second portions of opposite conductivity type, each one of the first portions extending across a first surface portion of said first semiconductor region, between a first region over a first channel region and a second region over a neighboring second channel region.
Claim 3
Dependent Claim
31 words
A device according to claim 1, wherein said second portions of the gate-electrode layer are formed by ion implantation at a dose of 10 11 to 10 13 /cm 2 .
Claim 4
Dependent Claim
23 words
A device according to claim 2, wherein said second regions are substantially square in shape when viewed from the top of the device.
Claim 5
Dependent Claim
23 words
A device according to claim 2, wherein said second regions are substantially rectangular in shape when viewed from the top of the device.
Claim 6
Independent Claim
37 words
A device according to claims 1, 2 or 3, wherein the portion of said insulation film disposed over said first surface portions of said first semiconductor region is thicker than the insulation film over said channel regions.
Claim 7
Dependent Claim
234 words
A metal-oxide-semiconductor device comprising: a first semiconductor region of a first conductive type having a first surface and a second surface; a plurality of second regions of a second conductive type at said first surface of said first semiconductor region, said second regions being substantially rectangular in shape; a third region of said first conductive type in each of said second regions; a plurality of channel regions formed between said third region and said first surface of said first semiconductor region; and a gate-electrode layer disposed on an insulation film over said channel regions and first surface portions of said first semiconductor region; wherein portions of said gate-electrode layer disposed over two adjacent channel regions and interposing first-surface portions of said first semiconductor region having a conductivity type opposite to the conductivity type of other portions of the gate-electrode layer, portions of the gate-electrode layer not disposed over said channel regions and interposing first-surface portions of said first semiconductor region are formed by ion implantation at a dose of 10 11 to 10 13 /cm 2 , and selected portions of the gate-electrode layer disposed over selected first-surface portions of said first semiconductor region, which surface portions are interposed between longer sides of two adjacent second regions, have a conductivity type opposite to the conductivity type of portions of the gate-electrode layer disposed over said channel regions along longer edge of said channel regions.
Claim 8
Dependent Claim
234 words
A metal-oxide-semiconductor device comprising: a first semiconductor region of a first conductive type having a first surface and a second surface; a plurality of second regions of a second conductive type at said first surface of said first semiconductor region, said second regions being substantially rectangular in shape; a third region of said first conductive type in each of said second regions; a plurality of channel regions formed between said third region and said first surface of said first semiconductor region; and a gate-electrode layer disposed on an insulation film over said channel regions and first surface portions of said first semiconductor region; wherein portions of said gate-electrode layer disposed over two adjacent channel regions and interposing first-surface portions of said first semiconductor region having a conductivity type opposite to the conductivity type of other portions of the gate-electrode layer, portions of the gate-electrode layer not disposed over said channel regions and interposing first-surface portions of said first semiconductor region are formed by ion implantation at a dose of 10 11 to 10 13 /cm 2 , and selected portions of the gate-electrode layer disposed over selected first-surface portions of said first semiconductor region, which surface portions are interposed between longer sides of two adjacent second regions, have a conductivity type opposite to the conductivity type of portions of the gate-electrode layer disposed over said channel regions along longer edge of said channel regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |