US5290709A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1992-04-09
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Granted: 1994-03-01
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Expires: 2012-04-09
Abstract
Abstract According to the present invention, in the ion implantation step in manufacturing a semiconductor device, a resist of a resist pattern formed on a portion of a semiconductor wafer is removed from the outer peripheral portion of the semiconductor wafer, and ion implantation is performed through the resist pattern. Since the resist is removed from the outer peripheral portion, a contact portion between a semiconductor wafer fixing portion of an ion implantation unit and the semiconductor wafer is conductive. Therefore, charges generated by the ion implantation escape from the wafer fixing portion, and the semiconductor wafer is not charged, thereby preventing electrostatic breakdown.
Inventors
- 👤 Akira Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:35
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/22; Y; Y10; Y10S; Y10S148/00; Y10S148/076; Y10S148/082; Y10S148/083
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
119 words
A method of manufacturing a semiconductor device comprising the steps of: coating an entire surface of a semiconductor wafer with an insulating resist; exposing and developing said coated insulating resist to form a resist pattern at an inner peripheral portion of said semiconductor wafer and to remove said insulating resist from an outer peripheral portion of said semiconductor wafer; the outer peripheral portion of said semiconductor wafer from which said insulating resist is removed being placed in surface contact with a fixing portion of an ion implantation unit, so that charges accumulated in said semiconductor wafer during an ion implantation step escape through said fixing portion; and performing ion implantation to said semiconductor wafer through said insulating resist pattern.
Claim 2
Independent Claim
119 words
A method of manufacturing a semiconductor device comprising the steps of: coating an entire surface of a semiconductor wafer with an insulating resist; exposing and developing said coated insulating resist to form a resist pattern at an inner peripheral portion of said semiconductor wafer and to remove said insulating resist from an outer peripheral portion of said semiconductor wafer; the outer peripheral portion of said semiconductor wafer from which said insulating resist is removed being placed in surface contact with a fixing portion of an ion implantation unit, so that charges accumulated in said semiconductor wafer during an ion implantation step escape through said fixing portion; and performing ion implantation to said semiconductor wafer through said insulating resist pattern.
Claim 3
Dependent Claim
29 words
A method according to claim 1, wherein formation of said resist pattern is performed simultaneously with removal of said resist from the outer peripheral portion of said semiconductor wafer.
References Cited (Backward Citations)
JPS60234318A
Cited
JPS62248223A
Cited
JPS63278325A
Cited
JPH01196817A
Cited
JPH0216737A
Cited
JPH0263116A
Cited
US5075240A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |