Method for data transmission over an internal bus of a workstation apparatus with an internal bus for implementing the method, and an adapter circuit for the internal bus

Claim 3

A method in accordance with claim 1, which further comprises providing adapter circuitry for each communication processing device (13, 14, 15, 16) operable to process only subframes in which the device destination address coded in the second header byte corresponds to the particular device destination address.

Claim 4

A method in accordance with claim 1, wherein each variable-length subframe has a maximum length of 32 bytes.

Claim 5

A method in accordance with claim 2, wherein each variable-length subframe has a maximum length of 32 bytes.

Claim 6

A method in accordance with claim 1, which comprises coding the first header byte of a subframe having zero data bytes with the value hexadecimal FF.

Claim 7

A method in accordance with claim 3, which comprises coding the first header byte of a subframe having zero data bytes with the value hexadecimal FF.

Claim 8

A serial bus apparatus internal to a computer workstation having a parallel system bus for interfacing the computer workstation with a plurality of data input/output/processing devices, said serial bus apparatus comprising: an internal serial bus (6) including an input-output data line (62), a frame synchronization line (64) and a bit clock line (63), said internal serial bus serving to interface with: a) a telephone line interface (10) via a first bus adapter circuit (1); b) a multi-protocol communication controller (13) connected to said workstation parallel system bus via a second bus adapter circuit (2) for interfacing a serial data communication channel to said parallel system bus; c) a serial interface (16) for at least one of a printer (17) and a scanner (18) via a third bus adapter circuit (3); d) an image processor (14) connected to said workstation parallel system bus for performing at least one of the functions of image compression, image decompression, decoding, encoding, or facsimile transmission via a fourth bus adapter circuit (4); and e) a voice processor (15) connected to said workstation parallel system bus for performing at least one of the functions of voice analysis, vocal control of peripheral equipment, voice synthesis via a fifth bus adapter circuit (5).

Claim 9

A serial bus apparatus internal to a computer workstation having a parallel system bus for interfacing the computer workstation with a plurality of data input/output/processing devices, said serial bus apparatus comprising: an internal serial bus (6) including an input-output data line (62), a frame synchronization line (64) and a bit clock line (63), said internal serial bus serving to interface with: a) a telephone line interface (10) via a first bus adapter circuit (1); b) a multi-protocol communication controller (13) connected to said workstation parallel system bus via a second bus adapter circuit (2) for interfacing a serial data communication channel to said parallel system bus; c) a serial interface (16) for at least one of a printer (17) and a scanner (18) via a third bus adapter circuit (3); d) an image processor (14) connected to said workstation parallel system bus for performing at least one of the functions of image compression, image decompression, decoding, encoding, or facsimile transmission via a fourth bus adapter circuit (4); and e) a voice processor (15) connected to said workstation parallel system bus for performing at least one of the functions of voice analysis, vocal control of peripheral equipment, voice synthesis via a fifth bus adapter circuit (5).

Claim 10

An adapter circuit for interfacing data in addressed subframe between a serial bus (6) internal to a workstation and a data input/output/processing device (13,14) having a particular device destination address and connected to a parallel system bus (20) of said workstation, and for providing at least two serial transmission/reception channels (A, B, C), said adapter circuit comprising: a) a transmission channel circuit (90) within each of said transmission/reception channels (A, B, C), and connected to said parallel system bus (20) through the device (13, 14), for processing data transmitted from said device (13, 14) via each of said at least two serial transmission/reception channels (A, B, C); b) a reception channel circuit (100) within each of said transmission/reception channels (A, B, C), and connected to said parallel system bus (20) through the device (13, 14), for processing data received by said device (13, 14) via each of said at least two serial transmission/reception channels (A, B, C); c) a register bank (86) of addressable five-bit registers connected to said transmission channel circuits (90) and to said reception channel circuits (100) for receiving data transmitted to and received from said device (13, 14) and for storing information denoting the states of said serial transmission/reception channels (A, B, C) as transmitting to or receiving from said device (13, 14); d) a subframe description circuit (891) connected to the internal serial bus (6) for providing timing signals derived in part from said serial bus (6) and for processing said timing signals to provide information denoting the states of said serial transmission/reception channels (A, B, C) to said register bank (86), said timing signals corresponding to at least the function of end of subframe; and e) subframe address enable and control circuitry (890) connected to said transmission channel circuits (90) and to said reception channel circuits (100) and to said register bank (86) for examining subframe addresses and for providing enabling and control signals to said register bank (86) corresponding to at least one of the functions of data reception enable, data transmission enable, end of transmission.

Claim 11

An adapter circuit for interfacing data in addressed subframe between a serial bus (6) internal to a workstation and a data input/output/processing device (13,14) having a particular device destination address and connected to a parallel system bus (20) of said workstation, and for providing at least two serial transmission/reception channels (A, B, C), said adapter circuit comprising: a) a transmission channel circuit (90) within each of said transmission/reception channels (A, B, C), and connected to said parallel system bus (20) through the device (13, 14), for processing data transmitted from said device (13, 14) via each of said at least two serial transmission/reception channels (A, B, C); b) a reception channel circuit (100) within each of said transmission/reception channels (A, B, C), and connected to said parallel system bus (20) through the device (13, 14), for processing data received by said device (13, 14) via each of said at least two serial transmission/reception channels (A, B, C); c) a register bank (86) of addressable five-bit registers connected to said transmission channel circuits (90) and to said reception channel circuits (100) for receiving data transmitted to and received from said device (13, 14) and for storing information denoting the states of said serial transmission/reception channels (A, B, C) as transmitting to or receiving from said device (13, 14); d) a subframe description circuit (891) connected to the internal serial bus (6) for providing timing signals derived in part from said serial bus (6) and for processing said timing signals to provide information denoting the states of said serial transmission/reception channels (A, B, C) to said register bank (86), said timing signals corresponding to at least the function of end of subframe; and e) subframe address enable and control circuitry (890) connected to said transmission channel circuits (90) and to said reception channel circuits (100) and to said register bank (86) for examining subframe addresses and for providing enabling and control signals to said register bank (86) corresponding to at least one of the functions of data reception enable, data transmission enable, end of transmission.

Claim 12

An adapter circuit in accordance with claim 8, wherein at least on register (R00, R01, R02) of said register bank (86) contains a subframe address which designates one of said transmission/reception channels, and an enable bit (VCA, VCB, VCC) which enables transmission or reception via at least one of said transmission/reception channels.

Claim 13

An adapter circuit in accordance with claim 8, wherein said transmission/reception channels are operable to selectively function in a transmission mode, and further wherein at least one register (R08, R09, R10) of said register bank (86) contains bits indicating whether said transmission/reception channels (A, B, C) operating in a transmission mode are idle or transmitting.

Claim 14

An adapter circuit in accordance with claim 9, wherein said transmission/reception channels are operable to selectively function in a transmission mode, and further wherein at least one register (R08, R09, R10) of said register bank (86) contains bits indicating whether said transmission/reception channels (A, B, C) operating in a transmission mode are idle or transmitting.

Claim 15

An adapter circuit in according with claim 8, wherein said selectively function in a reception mode, and further wherein at least one register (R12, R13, R14) of said register bank (86) contains bits indicating whether said transmission/reception channels (A, B, C) operating in the reception mode are idle or receiving.

Claim 16

An adapter circuit in accordance with claim 9, wherein said transmission/reception channels are operable to selectively function in a reception mode, and further wherein at least one register (R12, R13, R14) of said register bank (86) contains bit indicating whether said transmission/reception channels (A, B, C) operating in the reception mode are idle or receiving.

Claim 17

An adapter circuit in accordance with claim 8, wherein at least one register (R15) of said register bank (86) is a status register including information on transmission or reception synchronization and said subframe description circuit.

Claim 18

A method of data transmission in accordance with claim 2 further including the step of setting the eight variable length subframes to a maximum length of two bytes.

Claim 19

A method according to claim 2 further including the step of defining said communication frame as a 125 micro second frame.