US5287045A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fully digital apparatus for controlling operation of electric motor
Assignee: Toshiba Corp
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Filing: 1992-08-03
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Granted: 1994-02-15
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Expires: 2012-08-03
Abstract
Abstract A digital apparatus for controlling an operation of an electric motor capable of realizing a fully digital speed control without creating a severe restriction on data transfer and an excessive demand on the micro-processor. The apparatus includes a micro-processor for carrying out normal speed control processings at normal speed timings; a high speed digital processor for carrying out high speed control processings at high speed timings faster than the normal speed timings; and interface register for interfacing data transmission between the micro-processor and the high speed digital processor; and a timing circuit for receiving access signals from the micro-processor, and producing timing signals based on the high speed timings by using the access signals where the timing signals control timings of the data transmission through the interface register.
Inventors
- 👤 Soukichi Uehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:09
CPC Classifications
H; H02; H02P; H02P23/00; H02P23/0077
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
162 words
An apparatus for digitally controlling a speed of an electric motor, comprising: micro-processor means for carrying out low speed control processings at low speed timings; high speed digital processor means for carrying out high speed control processings at high speed timings faster than the low speed timings, the high speed digital processor means including, interface register means for interfacing data transmission between the micro-processor means and the high speed digital processor means, where data to be interfaced by the interface register means contain no information concerning timings of the data transmission through the interface register means; and timing circuit means for receiving access signals from the micro-processor means, and producing timing signals based on the high speed timings by using the access signals where the timing signals control the timings of the data transmission through the interface register means; and means for controlling the speed of the electric motor according to the low speed control processings and the high speed control processings.
Claim 2
Independent Claim
162 words
An apparatus for digitally controlling a speed of an electric motor, comprising: micro-processor means for carrying out low speed control processings at low speed timings; high speed digital processor means for carrying out high speed control processings at high speed timings faster than the low speed timings, the high speed digital processor means including, interface register means for interfacing data transmission between the micro-processor means and the high speed digital processor means, where data to be interfaced by the interface register means contain no information concerning timings of the data transmission through the interface register means; and timing circuit means for receiving access signals from the micro-processor means, and producing timing signals based on the high speed timings by using the access signals where the timing signals control the timings of the data transmission through the interface register means; and means for controlling the speed of the electric motor according to the low speed control processings and the high speed control processings.
Claim 3
Dependent Claim
39 words
The apparatus of claim 1, wherein the timing circuit means controls the timings of the data transmission through the interface register means to be different from timings at which data are updated in the high speed digital processor means.
Claim 4
Dependent Claim
48 words
The apparatus of claim 1, wherein the interface register means receives data from the micro-processor means at timings of the access signals from the micro-processor means, and outputs said data to the high speed digital processor means at timings of the timing signals from the timing circuit means.
Claim 5
Dependent Claim
48 words
The apparatus of claim 1, wherein the interface register means receives data from the high speed digital processor means at timings of the timing signals from the timing circuit means, and outputs said data to the micro-processor means at timings of the access signals from the micro-processor means.
Claim 6
Dependent Claim
60 words
The apparatus of claim 1, wherein the timing circuit means comprises: a D-Q flip flop circuit with a pre-set which receives the access signals, and produces a Q terminal output at a timing synchronized with the high speed timings; and a differentiating circuit which receives the Q terminal output of the D-Q flip flop circuit, and produces the timing signals.
Claim 7
Dependent Claim
26 words
The apparatus of claim 5, wherein the timing circuit means further comprises shift register means inserted between the D-Q flip flop circuit and the differentiating circuit.
Claim 8
Dependent Claim
21 words
The apparatus of claim 1, wherein the timing circuit means utilizes timing obtained by frequency multiplication of the high speed timings.
Claim 9
Dependent Claim
20 words
The apparatus of claim 1, wherein the high speed digital processor means includes at least one application specific integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |