US5285415A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data counting memory card and reader
Assignee: STMicroelectronics SA
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Filing: 1992-06-22
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Granted: 1994-02-08
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Expires: 2012-06-22
Abstract
Abstract An integrated circuit for a passive unit counting memory card comprises p levels (10, 11, 12) of data counting memory. The levels contain corresponding numbers of cases n 1 . . . n p , a write operation being achieved in a case of an upper rank level each time all the cases of the lower rank level have been enabled, the cases of the lower levels then being erased. The circuit comprises p-1 ghost levels (21, 22) identical to the p-1 upper rank levels of the p counting levels. The addressing logic of the ghost levels is such that the cases of ghost levels are addressed in write phase simultaneously with the cases of the corresponding counting levels and, after a write phase, are addressed in erase phase simultaneously with the cases of the levels of lower rank than the one that has just been enabled.
Inventors
- 👤 Eric Depret
- 👤 Laurent Sourgen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:51
CPC Classifications
G; G07; G07F; G07F7/00; G07F7/08; G07F7/10; G07F7/1008; G06; G06K; G06K19/00; G06K19/06; G06K19/067; G06K19/07; G06Q; G06Q20/00; G06Q20/30; G06Q20/34; G06Q20/341; G07F7/0806; G07F7/0813; G07F7/082; G07F7/0866; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C16/105
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
141 words
A passive unit counting integrated circuit for a portable support comprising: p memory levels for counting data containing corresponding numbers of memory cases n 1 . . . n p , a write operation being carried out for a case of an upper rank level when all cases of lower rank level have been enabled, said lower level cases being then disabled, (p-1) ghost levels identical to the p-1 upper rank levels of the p memory levels for counting, the addressing logic of the ghost levels being such that the cases of said ghost levels are addressed in a write phase simultaneously with the respective cases of the corresponding counting levels and, after a write phase, are addressed in an erase phase simultaneously with the cases of the memory levels of lower rank than the rank that has just been enabled.
Claim 2
Dependent Claim
141 words
A passive unit counting integrated circuit for a portable support comprising: p memory levels for counting data containing corresponding numbers of memory cases n 1 . . . n p , a write operation being carried out for a case of an upper rank level when all cases of lower rank level have been enabled, said lower level cases being then disabled, (p-1) ghost levels identical to the p-1 upper rank levels of the p memory levels for counting, the addressing logic of the ghost levels being such that the cases of said ghost levels are addressed in a write phase simultaneously with the respective cases of the corresponding counting levels and, after a write phase, are addressed in an erase phase simultaneously with the cases of the memory levels of lower rank than the rank that has just been enabled.
Claim 3
Dependent Claim
29 words
A circuit according to claim 1, comprising a read decoder associated with each memory level for simultaneously addressing, during write phases, the corresponding ghost level of a same rank.
Claim 4
Dependent Claim
26 words
A circuit according to claim 1, comprising a read decoder associated with each memory level for simultaneously addressing, during erase phases, the upper rank ghost level.
Claim 5
Dependent Claim
65 words
A reader associated with a portable support including an integrated circuit according to claim 1, comprising: means for initially reading all the memory cases of the ghost levels, and means responsive to a write operation in a case of a ghost level to simultaneously erase said case of the ghost level and the cases of the lower rank level of the memory levels for counting.
References Cited (Backward Citations)
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US4256955A
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US4367402A
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FR2600795A1
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US5033021A
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US5089959A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |