US5285172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror power amplifier with gain controlled by resistor-capacitor network
Assignee: Sony Corp
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Filing: 1992-09-02
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Granted: 1994-02-08
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Expires: 2012-09-02
Abstract
Abstract An amplifier in which a current mirror circuit 53 is formed of a transistor Q25 on the input side and a transistor Q26 on the output side. The base-emitter junction area of the transistor Q26 is set to be N (N>1) times as large as that of the transistor Q25. A parallel circuit of a resistor R25 and a capacitor C25 is connected between the base of the transistor Q25 and its bias point Q27. A resistor R26 is connected between the base of the transistor Q26 and the bias point Q27. The resistance value of the resistor R25 is set to be virtually N times as large as the resistance value of the resistor R26. When an input current i25 is supplied to the transistor Q25, an output current i26, which is N times as large as the input current, is obtained from the transistor Q26 on the output side, whereas the output current i26 is held lower than N times of the input current i25 when the frequency of the input current is high.
Inventors
- 👤 Taiwa Okanobu
- 👤 Hitoshi Tomiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:01
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/083; H03F3/00; H03F3/30; H03F3/3066
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
194 words
An amplifier comprising: a current mirror circuit having a transistor on an input side and a transistor on an output side, a base-emitter junction area of said transistor on the output side being N (N>1) times as large as a base-emitter junction area of said transistor on the input side; a parallel circuit formed of a first resistor and a capacitor connected between a base connection of said transistor on the input side and a source of bias for said transistor on the input side; and a second resistor connected between a base of said transistor on the output side and said source of bias, a resistance value of said first resistor being set to be substantially N times as large as a resistance value of said second resistor; whereby when an input current is supplied to said transistor on the input side, an output current amplified by a factor N is obtained from said transistor on the output side, and when the frequency of the input current and the output current is high, the output current is held lower than N times the input current by a decrease in impedance of said capacitor.
Claim 2
Dependent Claim
194 words
An amplifier comprising: a current mirror circuit having a transistor on an input side and a transistor on an output side, a base-emitter junction area of said transistor on the output side being N (N>1) times as large as a base-emitter junction area of said transistor on the input side; a parallel circuit formed of a first resistor and a capacitor connected between a base connection of said transistor on the input side and a source of bias for said transistor on the input side; and a second resistor connected between a base of said transistor on the output side and said source of bias, a resistance value of said first resistor being set to be substantially N times as large as a resistance value of said second resistor; whereby when an input current is supplied to said transistor on the input side, an output current amplified by a factor N is obtained from said transistor on the output side, and when the frequency of the input current and the output current is high, the output current is held lower than N times the input current by a decrease in impedance of said capacitor.
Claim 3
Dependent Claim
232 words
An amplifier comprising: a transistor on an input side and a transistor on an output side, a base-emitter junction area of said transistor on the output side being N (N>1) times as large as a base-emitter junction area of said transistor on the input side, and emitters of said transistors being connected to a source of reference potentials; a transistor for biasing, a base thereof being connected to a collector of said transistor on the input side and the emitter thereof being connected to said source of reference potential through a biasing resistor; a parallel circuit formed of a first resistor and a capacitor connected between a base of said transistor on the input side and the emitter of said transistor for biasing; and a second resistor connected between a base of said transistor on the output side and the emitter of said transistor for biasing, a resistance value of said first resistor being substantially N times as large as a resistance value of said second resistor; whereby when an input current is supplied to said transistor on the input side, an output current amplified by a factor N is obtained from said transistor on the output side, and when the frequency of the input current and the output current is high, the output current is held lower than N times said input current by a decrease in impedance of said capacitor.
Claim 4
Dependent Claim
232 words
An amplifier comprising: a transistor on an input side and a transistor on an output side, a base-emitter junction area of said transistor on the output side being N (N>1) times as large as a base-emitter junction area of said transistor on the input side, and emitters of said transistors being connected to a source of reference potentials; a transistor for biasing, a base thereof being connected to a collector of said transistor on the input side and the emitter thereof being connected to said source of reference potential through a biasing resistor; a parallel circuit formed of a first resistor and a capacitor connected between a base of said transistor on the input side and the emitter of said transistor for biasing; and a second resistor connected between a base of said transistor on the output side and the emitter of said transistor for biasing, a resistance value of said first resistor being substantially N times as large as a resistance value of said second resistor; whereby when an input current is supplied to said transistor on the input side, an output current amplified by a factor N is obtained from said transistor on the output side, and when the frequency of the input current and the output current is high, the output current is held lower than N times said input current by a decrease in impedance of said capacitor.
References Cited (Backward Citations)
US4866312A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-07 | 1997-08-09 | 1998-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-07 | 2001-08-09 | 2002-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-07 | 2005-08-09 | 2006-02-08 | $7700.00 | Window Closed / Lapsed |