Power and signal distribution in electronic packaging

Claim 2

An integrated circuit packaging substrate comprising: a plurality of dielectric layers, electric conductor planes disposed between adjacent dielectric layers, each said electric conductor plane electrically referenced to a ground plane through a dielectric layer, and, each of said electric conductor planes having at least two power conductors and at least one signal conductor.

Claim 3

The substrate of claim 1 including a power conductor adjacent each signal conductor.

Claim 4

The substrate of claim 2 wherein each said power conductor is 1-5 microns thick and 15-65 microns wide, each said signal conductor is 1-5 microns thick and 10 to 15 microns wide with spacing between power and signal conductors of 5 to 25 microns and with a dielectric layer thickness of about 15 microns.

Claim 5

In an electronic wiring interconnecting substrate wherein there are superimposed layers of dielectric material supporting planes of conductors and ground, the controlled impedance conductor network improvement comprising: at least one assembly of a first ground layer, a first layer of dielectric material with a first surface thereof in contact with said first ground layer, a first plane of parallel power and signal conductors in the -x- identification direction, in contact with the second and opposite surface of said first layer of dielectric material, and wherein said first plane of parallel conductors includes a plurality of at least first and second power conductors, each of said power conductors having adjacent thereto at least one signal conductor electrically referenced to said adjacent power conductor, a second layer of dielectric material having a first surface in contact with the conductors of said first plane of conductors, a second plane of power and signal conductors in the -y- identification direction in contact with the second and opposite surface of said second layer of dielectric material, and wherein said second plane of parallel conductors includes a plurality of at least first and second power conductors, each of said power conductors having adjacent thereto at least one signal conductor electrically referenced to said adjacent power conductor, a third layer of dielectric material having a first surface in contact with the conductors of said second plane of conductors, and a second ground layer in contact with the second and opposite surface of said third layer of dielectric material.

Claim 6

In an electronic wiring interconnecting substrate wherein there are superimposed layers of dielectric material supporting planes of conductors and ground, the controlled impedance conductor network improvement comprising: at least one assembly of a first ground layer, a first layer of dielectric material with a first surface thereof in contact with said first ground layer, a first plane of parallel power and signal conductors in the -x- identification direction, in contact with the second and opposite surface of said first layer of dielectric material, and wherein said first plane of parallel conductors includes a plurality of at least first and second power conductors, each of said power conductors having adjacent thereto at least one signal conductor electrically referenced to said adjacent power conductor, a second layer of dielectric material having a first surface in contact with the conductors of said first plane of conductors, a second plane of power and signal conductors in the -y- identification direction in contact with the second and opposite surface of said second layer of dielectric material, and wherein said second plane of parallel conductors includes a plurality of at least first and second power conductors, each of said power conductors having adjacent thereto at least one signal conductor electrically referenced to said adjacent power conductor, a third layer of dielectric material having a first surface in contact with the conductors of said second plane of conductors, and a second ground layer in contact with the second and opposite surface of said third layer of dielectric material.

Claim 7

The wiring improvement of claim 4 including said assembly positioned on a wiring substrate and supporting at least one active device.

Claim 8

The wiring improvement of claim 5 wherein each said power conductor is 1-5 microns thick and 5-65 microns wide, each said signal conductor is 1-5 microns thick and 10-15 microns wide with spacing between power and signal conductors of 5 to 25 microns and with a dielectric layer thickness of about 15 microns.

Claim 9

In an electronic wiring substrate of parallel layers of conductor planes and ground planes, a controlled impedance power and signal distribution grid improvement comprising: each plane of conductors having at least two power levels with parallel power conductors, each power conductor having adjacent thereto a signal conductor electrically referenced to said adjacent power conductor, each plane of conductors being referenced through one dielectric thickness to a ground plane and via interconnections joining the power conductors of each power level on each conductor plane and via interconnections joining the signal conductors on each conductor plane referenced to the corresponding power level.

Claim 10

In an electronic wiring substrate of parallel layers of conductor planes and ground planes, a controlled impedance power and signal distribution grid improvement comprising: each plane of conductors having at least two power levels with parallel power conductors, each power conductor having adjacent thereto a signal conductor electrically referenced to said adjacent power conductor, each plane of conductors being referenced through one dielectric thickness to a ground plane and via interconnections joining the power conductors of each power level on each conductor plane and via interconnections joining the signal conductors on each conductor plane referenced to the corresponding power level.

Claim 11

The power and signal grid improvement of claim 7 wherein said layers of dielectric material, conductor planes and ground planes are assembled in a thin film modular structure positioned on a wiring structure and supporting at least one active device.

Claim 12

The power and signal grid improvement of claim 8 wherein each said power conductor is 1-5 microns thick and 5-65 microns wide, each said signal conductor is 1-5 microns thick and 10-15 microns wide with spacing between power and signal conductors of 5 to 25 microns and with a dielectric layer thickness of about 15 microns.

Claim 13

An electronic wiring interconnecting substrate of superimposed dielectric layers supporting and separating planes of conductors and ground comprising: at least one of said planes of conductors including at least two power levels with parallel power conductors, each with at least one adjacent signal conductor, and a ground plane separated from said plane of conductors by a dielectric layer.

Claim 14

An electronic wiring interconnecting substrate of superimposed dielectric layers supporting and separating planes of conductors and ground comprising: at least one of said planes of conductors including at least two power levels with parallel power conductors, each with at least one adjacent signal conductor, and a ground plane separated from said plane of conductors by a dielectric layer.

Claim 15

In electronic packaging of the type wherein wiring in a supporting structure provides power and signal interconnection for active signal translating elements on said supporting structure, the improvement comprising: a signal and power distribution network in said wiring structure wherein each power conductor is electrically referenced to ground through a single dielectric thickness and each signal conductor is electrically referenced both by adjacent positioning to a power conductor supplying it and through a single dielectric thickness to ground.

Claim 16

In electronic packaging of the type wherein wiring in a supporting structure provides power and signal interconnection for active signal translating elements on said supporting structure, the improvement comprising: a signal and power distribution network in said wiring structure wherein each power conductor is electrically referenced to ground through a single dielectric thickness and each signal conductor is electrically referenced both by adjacent positioning to a power conductor supplying it and through a single dielectric thickness to ground.

Claim 17

The electronic packaging improvement of claim 11 wherein said signal and power distribution network is in a thin film module structure positioned on a wiring substrate and supporting semiconductor chips.

Claim 18

The electronic packaging improvement of claim 12 wherein each said power conductor is 1-5 microns thick and 5-65 microns wide, each said signal conductor is 1-5 microns thick and 10-15 microns wide with spacing between power and signal conductors of 5 to 25 microns and with a dielectric layer thickness of about 15 microns.