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US5283880A
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Method of fast buffer copying by utilizing a cache memory to accept a page of source buffer contents and then supplying these contents to a target buffer without causing unnecessary wait states
Assignee: Hewlett Packard Development Co LP
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Filing: 1991-01-02
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Granted: 1994-02-01
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Expires: 2011-01-02
Abstract
Abstract A method for performing buffer copy operations in a personal computer system utilizing paged memory mode architecture and having a cache memory. The contents of a first buffer are read into a microprocessor register and simultaneously written into a cache memory. The first buffer is then read again and written to a second buffer, with the actual data values being obtained from the cache memory. This method avoids excessive wait states associated with changing memory pages from the first buffer memory address to the second buffer memory address for each data value.
Inventors
- 👤 Fernando Marcias-Garza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0215; G06F12/08; G06F12/0802
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
In a computer system having a microprocessor having a plurality of registers, main memory utilizing paged mode memory devices, a memory controller, a cache memory and a cache memory controller, an improved method for copying information from a first buffer beginning at a first address in main memory, the first buffer having a size less than that of the cache memory, to a second buffer beginning at a second address in main memory, the steps comprising: (a) reading n bytes from the first buffer, where n is a word width; (b) writing said n bytes to a location which does not result in a page miss of the paged mode memory devices and simultaneously writing said n bytes into the cache memory; (c) performing steps (a) through (b) as a series of page hit read operations of the paged mode memory devices until the contents of the first buffer have been loaded into cache memory; (d) reading n bytes of the first buffer from the cache memory; (e) writing said n bytes to the second buffer address; and (f) performing steps (d) through (e) as a series of cache read hits and page write hits to the paged mode memory devices until the contents of the first buffer have been written from the cache memory to the second buffer.
Claim 2
Dependent Claim
219 words
In a computer system having a microprocessor having a plurality of registers, main memory utilizing paged mode memory devices, a memory controller, a cache memory and a cache memory controller, an improved method for copying information from a first buffer beginning at a first address in main memory, the first buffer having a size less than that of the cache memory, to a second buffer beginning at a second address in main memory, the steps comprising: (a) reading n bytes from the first buffer, where n is a word width; (b) writing said n bytes to a location which does not result in a page miss of the paged mode memory devices and simultaneously writing said n bytes into the cache memory; (c) performing steps (a) through (b) as a series of page hit read operations of the paged mode memory devices until the contents of the first buffer have been loaded into cache memory; (d) reading n bytes of the first buffer from the cache memory; (e) writing said n bytes to the second buffer address; and (f) performing steps (d) through (e) as a series of cache read hits and page write hits to the paged mode memory devices until the contents of the first buffer have been written from the cache memory to the second buffer.
Claim 3
Dependent Claim
39 words
The method of claim 1, wherein the operation of writing said n bytes to a location not resulting in a page miss of the paged mode memory devices includes writing said n bytes to a register in the microprocessor.
Claim 4
Dependent Claim
52 words
The method of claim 2, further including performing the following steps prior to step (a): storing the beginning memory address of the first buffer; determining the required number of read operations to read the first buffer n bytes at a time; and storing the required number of read operations to be performed.
Claim 5
Dependent Claim
119 words
The method of claim 3, wherein steps (a) through (c) further include: reading a bytes from the firs buffer from a current first buffer address; writing said n bytes into the register in the microprocessor, overwriting any prior contents of the register and simultaneously writing said n bytes into the cache memory at an address corresponding to the current first buffer address; determining if the required number of read operations have been performed; incrementing the current first buffer address by n bytes and decrementing the required number of read operations to be performed when the required number of read operations have not been completed; and performing the above steps until the required number of read operations has been performed.
Claim 6
Dependent Claim
127 words
The method of claim 4, further including the step of resetting the first buffer address to the beginning first address after step (c) and prior to step (d) and wherein the steps (e) through (g) further include: reading n bytes of the first buffer from a cache memory address corresponding to the current first buffer address; wiring said n bytes to a current second buffer address; determining if the required number operations have been performed; incrementing the current first buffer address and the current second buffer address by n bytes and decrementing the required number of read operations to be performed when the required number of read operations have not been performed; and performing the above steps until the required number of read operations have been performed.
Claim 7
Dependent Claim
32 words
The method of claim 4, further including performing the following steps prior to step (e): reading the first buffer beginning address; and reading the required number of read operations to be performed.
Claim 8
Dependent Claim
42 words
The method of claim 1, wherein writing said n bytes to a location which does not result in a page miss of the paged mode memory devices includes writing back to the first buffer address from which said n bytes were read.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-31 | 1997-08-02 | 1998-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-31 | 2001-08-02 | 2002-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-31 | 2005-08-02 | 2006-02-01 | $7700.00 | Window Closed / Lapsed |