Mode switching system for a pixel based display unit

Claim 2

In a pixel display system comprising a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to apply address words over a first channel in sequence to said palette random access memory to read out said values from said memory locations selected by said address words, means to generate a pixel based display in accordance with the values read out from said random access memory, and control means connected to receive multibit commands in time sequence over a second channel and responsive to a first time sequence of said commands to control the storing of new color values in said random access memory, one of said commands of said first time sequence including the address at which the new color is to be stored and other commands of said first time sequence identifying color components of said new color to be stored at the address, the improvement comprising mode switching means connected to receive said multibit commands and operating to switch the mode of operation of said pixel display system in response to a predetermined second time sequence of said commands, said predetermined second time sequence of commands being different than said first sequence of commands.

Claim 3

In a pixel display system as recited in claim 1, wherein said second channel comprises an I/O channel and further comprising a digital processor connected to said control means and said mode switching means by said I/O channel, said digital processor being operable to apply said commands to said control means and said mode switching means via said I/O channel, said control means being responsive to a third time sequence of said commands to read out color values from said random access memory and transmit the read out color values to said digital processor via said I/O channel, said third sequence of commands being different than said predetermined second sequence of commands.

Claim 4

In a pixel display system as recited in claim 2, wherein said predetermined second sequence of commands include commands of said first sequence and commands of said third sequence.

Claim 5

In a pixel display system as recited in claim 1, wherein said mode switching means is operable to switch the mode of operation of said pixel display system from one in which intensity values stored in said random access memory are represented by a first number of bits to a mode in which intensity values stored in said random access memory are represented by a second number of bits different than said first number of bits.

Claim 6

In a pixel display system as recited in claim 1, wherein said pixel display system has a conventional mode of operation in which it displays each pixel of the display in accordance with a color read out from said random access memory and a second mode of operation in which said pixel display system displays some pixels bridging boundaries of a displayed object as mixes of the colors on each side of said boundary, said mode switching means switching said pixel display system between said modes in response to said predetermined second sequence of commands.

Claim 7

In a pixel display system as recited in claim 1 including means to operate in a conventional first mode to display an image in which each pixel of the image is represented by a color read out from an address location in said random access memory, said pixel display system having second and third modes of operation and means operable when said pixel display system is in said second and third modes of operation to display an image in which pixels bridging a boundary of an object to be displayed are displayed as mixes of colors stored in said random access memory corresponding to the colors on each side of said boundary in said image, said mix values being represented in said address words in different ways in said second and third modes, said mode switching means switching said pixel display system to said second mode of operation in response to said predetermined sequence of commands containing a first predetermined data value in one of said commands and switching said display system to said third mode in response to said predetermined second sequence of commands containing a second predetermined data value in one of said commands.

Claim 8

In a pixel display system as recited in claim 1, wherein said commands in second sequence contains data values and wherein said mode switching means will switch said pixel display system from a first mode to a second mode of operation only if the commands of said second sequence contain predetermined data values.

Claim 9

In a pixel display system as recited in claim 7, wherein said mode switching means is operable to switch said pixel display system from said first mode of operation to a third mode of operation only if said second sequence of commands contains a second set of predetermined data values, one of which is different than said first mentioned set of predetermined data values.

Claim 10

In a pixel display system as recited in claim 1, wherein said palette random access memory, said control means and said mode switching means are integrated into a single integrated circuit chip.

Claim 11

In a pixel display system comprising a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to apply address words in sequence to said palette random access memory to read out said values from said memory locations selected by said address words, means to generate a pixel based display in accordance with the values read out from said random access memory, control means, and a digital processor connected to said control means to apply multibit commands in sequence to said control means, said control means being responsive to a first sequence of said commands to control the storing of new color values in said random access memory and responsive to a second sequence of commands to read out color values from said random access memory and transmit the read out color values to said digital processor, the improvement comprising control means connected to receive said multibit commands and operating to control said pixel based display in response to a predetermined third sequence of said commands including commands of said first sequence and of said second sequence.

Claim 12

In a pixel display system comprising a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to apply address words in sequence to said palette random access memory to read out said values from said memory locations selected by said address words, means to generate a pixel based display in accordance with the values read out from said random access memory, control means, and a digital processor connected to said control means to apply multibit commands in sequence to said control means, said control means being responsive to a first sequence of said commands to control the storing of new color values in said random access memory and responsive to a second sequence of commands to read out color values from said random access memory and transmit the read out color values to said digital processor, the improvement comprising control means connected to receive said multibit commands and operating to control said pixel based display in response to a predetermined third sequence of said commands including commands of said first sequence and of said second sequence.

Claim 13

In a pixel display system comprising a digital processor and a pixel decoder palette connected to said digital processor, said pixel decoder palette including a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to receive address words in sequence and apply said address words sequentially to said palette random access memory to read out said values from said memory locations selected by said address words, and means to generate a pixel based display in accordance with the values read out from said random access memory and I/O control means connected to receive commands in sequence from said digital processor, said I/O control means being responsive to a first sequence of commands to control the storing of new color values in said random access memory and responsive to a second sequence of commands to read out color values from said random access memory and transmit the read out values to said digital processor, the improvement comprising second control means connected to receive said multibit commands and operating to control said pixel decoder palette in response to a predetermined third sequence of commands including commands of said first sequence and of said second sequence.

Claim 14

In a pixel display system comprising a digital processor and a pixel decoder palette connected to said digital processor, said pixel decoder palette including a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to receive address words in sequence and apply said address words sequentially to said palette random access memory to read out said values from said memory locations selected by said address words, and means to generate a pixel based display in accordance with the values read out from said random access memory and I/O control means connected to receive commands in sequence from said digital processor, said I/O control means being responsive to a first sequence of commands to control the storing of new color values in said random access memory and responsive to a second sequence of commands to read out color values from said random access memory and transmit the read out values to said digital processor, the improvement comprising second control means connected to receive said multibit commands and operating to control said pixel decoder palette in response to a predetermined third sequence of commands including commands of said first sequence and of said second sequence.

Claim 15

In a pixel based display system as recited in claim 11 wherein at least one command of said third sequence includes an information byte containing information and wherein said second control means controls said pixel decoder palette in accordance with the information in said information byte.

Claim 16

In a pixel decoder system as recited in claim 11, wherein said first sequence comprises a write addressing command for selecting an address location in said palette random access memory for storing of new color followed by three write color commands containing the color values to be stored in the address location selected by the write addressing command, wherein said second sequence comprises a read addressing command for selecting an address location in said palette RAM to be read out followed by three read color commands causing color values to be read from the address location selected by said read addressing command, and wherein said third sequence comprises the following commands in sequence: a first read addressing command containing a predetermined address, first, second and third write color commands containing predetermined data values, a second read address command containing said predetermined address, fourth, fifth and sixth write color commands containing predetermined values, a third read addressing command containing said predetermined address, and seventh and eighth write color commands containing predetermined values.

Claim 17

A plug-to-plug compatible pixel decoder palette comprising a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to receive applied address words in sequence and apply said address words to said palette random access memory to read out said values from said memory locations selected by said address words, means responsive to the values read out from said address memory to generate color video signals for generating a pixel based display in accordance with the values read out from said random access memory, said means to generate analog video signals effecting the display of some pixels bridging boundaries of a displayed objects as mixes of colors on each side of said boundary, wherein said random access memory, said means to receive said address words in sequence, and said means to generate analog signals are integrated into a single integrated circuit chip, said integrated circuit chip including I/O control means for receiving multibit commands transmitted on an I/O channel in sequence and responsive to a first time sequence of said commands to control the storing of new color values in said random access memory, and second control means connected to receive said multibit commands transmitted on said I/O channel and operating to control said integrated circuit chip in response to a plurality of commands in a second time sequence of commands different than said first sequence of commands in accordance with information received in said second sequence of commands.

Claim 18

A plug-to-plug compatible pixel decoder palette comprising a palette random access memory having a multiplicity of memory locations, each capable of storing a value representing a color to be displayed, means to receive applied address words in sequence and apply said address words to said palette random access memory to read out said values from said memory locations selected by said address words, means responsive to the values read out from said address memory to generate color video signals for generating a pixel based display in accordance with the values read out from said random access memory, said means to generate analog video signals effecting the display of some pixels bridging boundaries of a displayed objects as mixes of colors on each side of said boundary, wherein said random access memory, said means to receive said address words in sequence, and said means to generate analog signals are integrated into a single integrated circuit chip, said integrated circuit chip including I/O control means for receiving multibit commands transmitted on an I/O channel in sequence and responsive to a first time sequence of said commands to control the storing of new color values in said random access memory, and second control means connected to receive said multibit commands transmitted on said I/O channel and operating to control said integrated circuit chip in response to a plurality of commands in a second time sequence of commands different than said first sequence of commands in accordance with information received in said second sequence of commands.

Claim 19

A pixel decoder palette as recited in claim 14, wherein said information is contained in a predetermined byte of said second sequence and wherein said control means controls the operation of said integrated circuit chip in accordance with the information in said predetermined byte.