US5282206A
Expired / Lapsed
US
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Synchronization circuit for establishing frame synchronism using pointers in a digital transmission system
Assignee: Fujitsu Ltd
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Filing: 1992-12-03
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Granted: 1994-01-25
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Expires: 2012-12-03
Abstract
Abstract A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse signal being synchronized with the beginning of the information part.
Inventors
- 👤 Tomohiro Ishihara
- 👤 Haruo Yamashita
- 👤 Toshiyuki Sudo
- 👤 Ryuichi Kondo
- 👤 Takaaki Wakisaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 06:19
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608; H04J2203/00; H04J2203/0001; H04J2203/0089
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
231 words
A synchronization circuit for a digital transmission system, the circuit comprising: a first circuit block inputted with and operating in synchronism with a first clock signal; and a second circuit block inputted with and operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal, wherein the first circuit block comprises: frame synchronizing means for detecting a framing pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part; synchronizing means, coupled to the frame synchronizing means, for generating, from the framing pattern, a synchronizing control signal for synchronizing operation of the second circuit block with operation of the first circuit block; and pulse generating means, coupled to the synchronizing means, for generating a first frame pulse signal from the first clock signal, and wherein the second circuit block comprises information part detecting means, coupled to the synchronizing means and the pulse generating means, for generating from the second clock signal and the synchronizing control signal a second frame pulse signal having a frequency lower than that of the first frame pulse signal, and transmitting the second frame pulse signal to the pulse generating means, the first frame pulse signal being synchronized with the beginning of the information part.
Claim 2
Dependent Claim
231 words
A synchronization circuit for a digital transmission system, the circuit comprising: a first circuit block inputted with and operating in synchronism with a first clock signal; and a second circuit block inputted with and operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal, wherein the first circuit block comprises: frame synchronizing means for detecting a framing pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part; synchronizing means, coupled to the frame synchronizing means, for generating, from the framing pattern, a synchronizing control signal for synchronizing operation of the second circuit block with operation of the first circuit block; and pulse generating means, coupled to the synchronizing means, for generating a first frame pulse signal from the first clock signal, and wherein the second circuit block comprises information part detecting means, coupled to the synchronizing means and the pulse generating means, for generating from the second clock signal and the synchronizing control signal a second frame pulse signal having a frequency lower than that of the first frame pulse signal, and transmitting the second frame pulse signal to the pulse generating means, the first frame pulse signal being synchronized with the beginning of the information part.
Claim 3
Dependent Claim
34 words
The synchronization circuit as claimed in claim 1, wherein the information part detecting means comprises counter means for counting a number of pulses of the second clock signal after receiving the synchronizing control signal.
Claim 4
Dependent Claim
36 words
The synchronization circuit as claimed in claim 1, wherein the information part detecting means comprises means for generating the second frame pulse signal having a pulse width corresponding to a period of the first clock signal.
Claim 5
Dependent Claim
163 words
The synchronization circuit as claimed in claim 1, wherein the synchronizing means of the first circuit block comprises: first counter means, coupled to the frame synchronizing means, for counting a number of bytes in a frame of the input data in accordance with the framing pattern; pointer information latch means, operatively coupled to the first counter means, for latching the pointer information in accordance with a counter value indicated by the first counter means; second counter means, coupled to the first counter means, for counting a number of bytes in the information part of the input data in synchronism with the first clock signal; comparator means, coupled to the pointer information latch means and the second counter means, for detecting whether or not a difference between a counter value indicated by the second counter means and a value indicated by the pointer information latch means has become equal to a predetermined value and for generating the synchronizing control signal when detecting said difference.
Claim 6
Dependent Claim
24 words
The synchronization circuit as claimed in claim 4, further comprising frequency divider means for generating the second clock signal from the first clock signal.
Claim 7
Dependent Claim
20 words
The synchronization circuit as claimed in claim 4, wherein the frequency divider means is provided in the first circuit block.
Claim 8
Dependent Claim
173 words
The synchronization circuit as claimed in claim 1, wherein the synchronizing means of the first circuit block comprises: first counter means, coupled to the frame synchronizing means, for counting a number of bytes in a frame of the input data in accordance with the synchronous pattern, and pointer information latch means, operatively coupled to the first counter means, for latching the pointer information in accordance with a counter value indicated by the first counter means, and wherein the second circuit block further comprises: second counter means, coupled to the first counter means, for counting a number of bytes in the information part of the input data in synchronism with the second clock signal, and comparator means, coupled to the pointer information latch means and the second counter means, for detecting whether or not a difference between a counter value indicated by the second counter means and a value indicated by the pointer information latch means has become equal to a predetermined value and for generating the synchronizing control signal when detecting said difference.
Claim 9
Dependent Claim
24 words
The synchronization circuit as claimed in claim 7, further comprising frequency divider means for generating the second clock signal from the first clock signal.
Claim 10
Dependent Claim
20 words
The synchronization circuit as claimed in claim 7, wherein the frequency divider means is provided in the first circuit block.
Claim 11
Dependent Claim
180 words
The synchronization circuit as claimed in claim 1, wherein the second circuit block comprises first counter means, coupled to the frame synchronizing means, for counting, in synchronism with the second clock signal, a number of bytes in a frame of the input data in accordance with the synchronous pattern and the synchronizing means of the first circuit block comprises pointer information latch means, operatively coupled to the first counter means, for latching the pointer information in accordance with a latch timing signal, and wherein the second circuit block further comprises: second counter means, coupled to the first counter means, for counting a number of bytes in the information part of the input data in synchronism with the second clock signal, and comparator means, coupled to the pointer information latch means and the second counter means, for detecting whether or not a difference between a counter value indicated by the second counter means and a value indicated by the pointer information latch means has become equal to a predetermined value and for generating the synchronizing control signal when detecting said difference.
Claim 12
Dependent Claim
45 words
The synchronization circuit as claimed in claim 10, wherein the first circuit block comprises means for generating a latch timing signal on the basis of a counter value indicated by the first counter means, said latch timing signal being synchronized with the first clock signal.
Claim 13
Dependent Claim
24 words
The synchronization circuit as claimed in claim 10, further comprising frequency divider means for generating the second clock signal from the first clock signal.
Claim 14
Dependent Claim
20 words
The synchronization circuit as claimed in claim 10, wherein the frequency divider means is provided in the first circuit block.
Claim 15
Dependent Claim
167 words
The synchronization circuit as claimed in claim 1, wherein the second circuit block comprises: first counter means, coupled to the frame synchronizing means, for counting, in synchronism with the second clock signal, a number of bytes in a frame of the input data in accordance with the forming pattern; pointer information latch means, operatively coupled to the first counter means, for latching the pointer information in accordance with a counter value indicated by the first counter means; second counter means, coupled to the first counter means, for counting a number of bytes in the information part of the input data in synchronism with the second clock signal; and comparator means, coupled to the pointer information latch means and the second counter means, for detecting whether or not a difference between a counter value indicated by the second counter means and a value indicated by the pointer information latch means has become equal to a predetermined value and for generating the synchronizing control signal when detecting said difference.
Claim 16
Dependent Claim
24 words
The synchronization circuit as claimed in claim 14, further comprising frequency divider means for generating the second clock signal from the first clock signal.
Claim 17
Dependent Claim
20 words
The synchronization circuit as claimed in claim 14, wherein the frequency divider means is provided in the first circuit block.
Claim 18
Dependent Claim
25 words
The synchronous circuit as claimed in claim 1, and further comprising frequency divider means for generating the second clock signal from the first clock signal.
Claim 19
Dependent Claim
20 words
The synchronous circuit as claimed in claim 17, wherein the frequency divider means is provided in the first circuit block.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-24 | 1997-07-26 | 1998-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-24 | 2001-07-26 | 2002-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-24 | 2005-07-26 | 2006-01-25 | $7700.00 | Window Closed / Lapsed |