Power semiconductor device having gate structure in trench

Claim 1

A power MOS semiconductor device, comprising: a body of semiconductor material including a first semiconductor layer of a first conductivity type and a substrate having an impurity concentration, said first semiconductor layer having an impurity concentration lower than said impurity concentration of said substrate; a second semiconductive layer of a second conductivity type having a high impurity concentration and disposed in said first semiconductor layer to provide a channel; a third semiconductive layer of said first conductivity type having a high impurity concentration and disposed in said second semiconductor layer; a trench disposed in said first semiconductor layer across said second and third semiconductor layers, said trench having a bottom and a depth deep enough to reduce an electric field concentration at said bottom of said trench; a buried layer of said first conductivity type disclosed in said first semiconductor layer, said buried layer contacting said substrate and being located between said bottom and said trench and said substrate, said buried layer having an impurity concentration approximately in the range of 5×10 15 cm -3 to 1×10 17 cm -3 ; a gate insulating film covering a surface of said trench and extending to a surface of said third semiconductor layer; and a gate electrode layer provided on said gate insulating film.