Jitter correction circuit for reducing jitter components of a luminance signal in video information compression

Claim 2

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a system clock signal locked to burst components of the video signal; second means for subjecting a first luminance signal in the video signal to phase interpolation to convert the first luminance signal to a second luminance signal; a memory; third means for selectively storing the second luminance signal into the memory to compress the second luminance signal; and fourth means for shifting a compressed luminance signal outputted from the memory by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than one fourth of a 1-clock period of the system clock signal.

Claim 3

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a first system clock signal locked to burst components of the video signal, the first system clock signal having a frequency equal to four times a chrominance subcarrier frequency of the video signal; second means for subjecting a first luminance signal in the video signal to phase interpolation in response to a second system clock signal to convert the first luminance signal to a second luminance signal, the second system clock signal having a frequency equal to eight times the chrominance subcarrier frequency of the video signal; a memory; third means for selectively storing the second luminance signal into the memory in response to the second system clock signal to compress the second luminance signal; and fourth means for shifting a compressed luminance signal outputted from the memory by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than two fourths of a 1-clock period of the second system clock signal.

Claim 4

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a first system clock signal locked to burst components of the video signal, the first system clock signal having a frequency equal to four times a chrominance subcarrier frequency of the video signal; second means for subjecting a first luminance signal in the video signal to phase interpolation in response to a second system clock signal to convert the first luminance signal to a second luminance signal, the second system clock signal having a frequency equal to eight times the chrominance subcarrier frequency of the video signal; a memory; third means for selectively storing the second luminance signal into the memory in response to the second system clock signal to compress the second luminance signal; and fourth means for shifting a compressed luminance signal outputted from the memory by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than two fourths of a 1-clock period of the second system clock signal.

Claim 5

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a first system clock signal locked to burst components of the video signal, and for generating data which represents the detected phase difference and which has an LSB to an MSB, the first system clock signal having a frequency equal to four times a chrominance subcarrier frequency of the video signal; second means for generating a horizontal reset pulse signal in response to the horizontal sync signal; third means synchronized with the horizontal reset pulse signal for subjecting a first luminance signal in the video signal to phase interpolation in response to a second system clock signal to convert the first luminance signal to a second luminance signal, the second system clock signal having a frequency equal to eight times the chrominance subcarrier frequency of the video signal; a memory; fourth means synchronized with the horizontal reset pulse signal for selectively storing the second luminance signal into the memory in response to the second system clock signal to compress the second luminance signal; a 1-clock delay element for shifting a timing of the horizontal reset pulse signal by a period corresponding to a 1-clock period of the second system clock signal when the MSB of the phase difference data is "1"; and fifth means for shifting a compressed luminance signal outputted from the memory by a period which is responsive to the LSB to an MSB-1 of the phase difference data and which is equal to or shorter than one fourth of the 1-clock period of the second system clock signal.

Claim 6

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a first system clock signal locked to burst components of the video signal, and for generating data which represents the detected phase difference and which has an LSB to an MSB, the first system clock signal having a frequency equal to four times a chrominance subcarrier frequency of the video signal; second means for generating a horizontal reset pulse signal in response to the horizontal sync signal; third means synchronized with the horizontal reset pulse signal for subjecting a first luminance signal in the video signal to phase interpolation in response to a second system clock signal to convert the first luminance signal to a second luminance signal, the second system clock signal having a frequency equal to eight times the chrominance subcarrier frequency of the video signal; a memory; fourth means synchronized with the horizontal reset pulse signal for selectively storing the second luminance signal into the memory in response to the second system clock signal to compress the second luminance signal; a 1-clock delay element for shifting a timing of the horizontal reset pulse signal by a period corresponding to a 1-clock period of the second system clock signal when the MSB of the phase difference data is "1"; and fifth means for shifting a compressed luminance signal outputted from the memory by a period which is responsive to the LSB to an MSB-1 of the phase difference data and which is equal to or shorter than one fourth of the 1-clock period of the second system clock signal.

Claim 7

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a system clock signal locked to burst components of the video signal; second means for subjecting a first luminance signal in the video signal to phase interpolation to convert the first luminance signal to a second luminance signal; third means for shifting the second luminance signal by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than one fourth of a 1-clock period of the system clock signal; a memory; and fourth means for selectively storing an output signal from the third means into the memory to compress the output signal from the third means.

Claim 8

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a system clock signal locked to burst components of the video signal; second means for subjecting a first luminance signal in the video signal to phase interpolation to convert the first luminance signal to a second luminance signal; third means for shifting the second luminance signal by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than one fourth of a 1-clock period of the system clock signal; a memory; and fourth means for selectively storing an output signal from the third means into the memory to compress the output signal from the third means.

Claim 9

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a system clock signal locked to burst components of the video signal; second means for shifting a first luminance signal in the video signal by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than one third of a 1-clock period of the system clock signal; third means for subjecting an output signal from the second means to phase interpolation to convert the output signal from the second means to a second luminance signal; a memory; and fourth means for selectively storing the second luminance signal into the memory to compress the second luminance signal.

Claim 10

A jitter correction circuit comprising: first means for detecting a phase difference between a horizontal sync signal in a video signal and a system clock signal locked to burst components of the video signal; second means for shifting a first luminance signal in the video signal by a period which is responsive to the phase difference detected by the first means and which is equal to or shorter than one third of a 1-clock period of the system clock signal; third means for subjecting an output signal from the second means to phase interpolation to convert the output signal from the second means to a second luminance signal; a memory; and fourth means for selectively storing the second luminance signal into the memory to compress the second luminance signal.