Clock recovery circuit with memory storage level comparison with high, medium and low thresholds

Claim 1

A sampling clock recovery circuit for receiving a coded image signal sampled at a sampling rate and transmitted at a line clock rate through a communication channel, said coded image signal containing a signal indicating a differential sampling clock rate representative of a frequency variation of said sampling rate, said sampling clock recovery circuit comprising: a first-in-first-out memory; means for driving a write clock of said first-in-first-out memory for writing the received coded image signal on a bit-parallel word basis into said first-in-first-out memory; a frequency correcting circuit including means for detecting a storage level of said first-in-first-out memory, comparing the storage level with an uppermost reference range, a higher middle reference range, a lower middle reference range and a lowermost reference range, and generating a first positive trimming value when the storage level is in said uppermost reference range, a second positive trimming value when the storage level is in said higher middle reference range, a first negative trimming value when the storage level is in said lower middle reference range, and a second negative trimming value when the storage level is in said lowermost reference range; and a local sampling clock generator including an adder for combining said signal indicating a differential sampling clock rate and one of said trimming values to produce a signal indicating a corrected differential sampling clock rate, means for detecting a frequency variation of said line clock rate to produce a signal indicating a differential line clock rate and subtractively combining the signal indicating a differential line clock rate with said signal indicating a corrected differential sampling clock rate to produce a difference signal, an integrator for integrating said difference signal, and a voltage-controlled oscillator responsive to an output signal of said integrator for driving a read clock of said first-in-first-out memory for reading the coded image signal therefrom on a bit-parallel word basis.