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US5274342A Expired / Lapsed US ⏱️ 0.0 years remaining

Microwave monolithic integrated circuit (MMIC) including distributed cascode bipolar transistor amplifier unit

Assignee: Raytheon Co
•
Filing: 1992-02-28
•
Granted: 1993-12-28
•
Expires: 2012-02-28
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Abstract

Abstract A microwave monolithic integrated circuit (MMIC) (40), includes a substrate (60), and an input bus (62), output bus (64), ground bus (66) and bias bus (68) formed as striplines of a four-line coplanar waveguide on the substrate (60) with the input bus (62) and output bus (64) disposed between the ground bus (66) and bias bus (68). A plurality of spatially distributed cascode amplifier units (43) are formed on the substrate (60), each including an input heterojunction bipolar transistor (HBT) (42) connected in a common-emitter configuration, and an output HBT (44) connected in a common-base configuration. The input HBT (42) has an emitter (E 1 ) connected to the ground bus (66), a base (B 1 ) connected to the input bus (62) and a collector (C 1 ). The output HBT (44) has an emitter (E 2 ) connected to the collector (C 1 ) of the input HBT (42), a base (B 2 ) connected to the bias bus (68) and a collector (C 2 ) connected to the output bus (64). The distributed amplifier arrangement enables the HBTs (42,44) to operate with balanced electrical parameters and high thermal isolation and heat dissipation.

Inventors

  • 👤 Cheng P. Wen
  • 👤 Chan S. Wu
  • 👤 Cheng K. Pao

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 16:08
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/22; H03F3/00; H03F3/60; H03F3/605

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 141 words
A distributed cascode amplifier, comprising an input bus; an output bus; a bias bus; a ground bus; a plurality of cascode amplifier units, each including; a first transistor having an emitter connected to the ground bus, a base connected to the input bus and a collector; a second transistor having an emitter connected to the collector of the first transistor, a base connected to the bias bus and a collector connected to the output bus; and a substrate, in which: the input bus, output bus, bias bus, ground bus and amplifier units are formed on the substrate; and the input bus, output bus, bias bus and ground bus extend substantially parallel to each other as striplines of a four-line coplanar waveguide with the input bus and output bus disposed between the bias bus and ground bus and being electrically shielded thereby.
Claim 2
Dependent Claim 141 words
A distributed cascode amplifier, comprising an input bus; an output bus; a bias bus; a ground bus; a plurality of cascode amplifier units, each including; a first transistor having an emitter connected to the ground bus, a base connected to the input bus and a collector; a second transistor having an emitter connected to the collector of the first transistor, a base connected to the bias bus and a collector connected to the output bus; and a substrate, in which: the input bus, output bus, bias bus, ground bus and amplifier units are formed on the substrate; and the input bus, output bus, bias bus and ground bus extend substantially parallel to each other as striplines of a four-line coplanar waveguide with the input bus and output bus disposed between the bias bus and ground bus and being electrically shielded thereby.
Claim 3
Dependent Claim 40 words
An amplifier as in claim 1, further comprising capacitance means connected between the bias bus and the ground bus and having a value of capacitance selected to provide a predetermined low value of capacitive reactance at a predetermined operating frequency.
Claim 4
Dependent Claim 22 words
An amplifier as in claim 1, in which the first and second transistors of each amplifier unit are heterojunction bipolar transistors (HBTs).
Claim 5
Dependent Claim 71 words
An amplifier as in claim 1, in which each amplifier unit further comprises; a first stripline connecting the collector of the first transistor to the emitter of the second transistor; a first airbridge extending over the input bus and connecting the emitter of the first transistor to the ground bus; and a second airbridge extending over the output bus and connecting the base of the second transistor to the bias bus.
Claim 6
Dependent Claim 46 words
An amplifier as in claim 4, in which each amplifier unit further comprises a capacitor connected between the emitter of the first transistor and the second airbridge and having a capacitance selected to provide a predetermined low value of capacitive reactance at a predetermined operating frequency.
Claim 7
Dependent Claim 53 words
An amplifier as in claim 5, in which: the capacitor has first and second plates; and each amplifier unit further comprises: a second stripline connecting the emitter of the first transistor to the first plate of the capacitor; and a third stripline connecting the second airbridge to the second plate of the capacitor.

References Cited (Backward Citations)

US3443238A Cited
US4250463A Cited
US5066926A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-12-27 1997-06-28 1997-12-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-12-27 2001-06-28 2001-12-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-12-27 2005-06-28 2005-12-28 $7700.00 Window Closed / Lapsed

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