US5272676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: Micron Memory Japan Ltd
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Filing: 1991-11-06
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Granted: 1993-12-21
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Expires: 2011-11-06
Abstract
Abstract The self-refresh operation of one round of a RAM using dynamic memory cells is accomplished on the basis of the periodic pulses which are formed by an oscillating circuit substantially having no temperature dependency, and the self-refresh period is controlled by a timer circuit using a time constant circuit corresponding to the temperature dependency of the data storage in the memory cells. The operating voltage or boosted output voltage is monitored to switch the circuit operation for generating a plurality kinds of boosted voltages rising sequentially two and three times so that the boosted voltage may be a desired voltage. A control voltage to be fed to the gate of a MOSFET connected between the substrate and the earth potential of the circuit is generated by a dummy substrate voltage generator having a leakage current path varying to follow the fluctuations in a supply voltage.
Inventors
- 👤 Shoji Kubono
- 👤 Hiroshi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:38
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40626; G11C11/40615; G11C5/00; G11C5/14; G11C5/145
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
196 words
A semiconductor memory comprising: a memory array including a plurality of word lines, a plurality of data lines and a plurality of memory cells each having a MOSFET and a capacitor; refresh means for outputting a refresh instructing signal for refreshing each of said memory cells; and control signal generating means responsive to said refresh instructing signal for generating a refresh controlling signal, wherein said refresh means includes: first refresh signal outputting means for outputting a first refresh timing signal for a predetermined period; a dummy cell having a plurality of MOSFETs and a capacitor which has a capacity smaller than the total capacity of the capacitor provided for the sources of said MOSFETs; a comparator for comparing a voltage held in the capacitor of said dummy cell and a predetermined reference voltage; a second refresh signal outputting means responsive to the output signal of said comparator for outputting a second refresh timing signal when said comparator outputs a signal indicating that the held voltage value of said capacitor is lower than said predetermined reference voltage value; and signal generating means responsive to said first and second refresh timing signals for generating said refresh instructing signal.
Claim 2
Dependent Claim
196 words
A semiconductor memory comprising: a memory array including a plurality of word lines, a plurality of data lines and a plurality of memory cells each having a MOSFET and a capacitor; refresh means for outputting a refresh instructing signal for refreshing each of said memory cells; and control signal generating means responsive to said refresh instructing signal for generating a refresh controlling signal, wherein said refresh means includes: first refresh signal outputting means for outputting a first refresh timing signal for a predetermined period; a dummy cell having a plurality of MOSFETs and a capacitor which has a capacity smaller than the total capacity of the capacitor provided for the sources of said MOSFETs; a comparator for comparing a voltage held in the capacitor of said dummy cell and a predetermined reference voltage; a second refresh signal outputting means responsive to the output signal of said comparator for outputting a second refresh timing signal when said comparator outputs a signal indicating that the held voltage value of said capacitor is lower than said predetermined reference voltage value; and signal generating means responsive to said first and second refresh timing signals for generating said refresh instructing signal.
Claim 3
Dependent Claim
18 words
A semiconductor memory according to claim 1, wherein said second refresh signal outputting means includes a counter circuit.
Claim 4
Dependent Claim
16 words
A semiconductor memory according to claim 2, wherein said counter circuit has a plurality of flip-flops.
Claim 5
Dependent Claim
42 words
A semiconductor memory according to claim 3, further comprising: a first address terminal group fed with an address for selecting one of said word lines; and a second address terminal group fed with an address for selecting one of said data lines.
Claim 6
Dependent Claim
35 words
A semiconductor memory system according to claim 1, wherein the capacity of said dummy cell capacitor is smaller by one figure than said total capacity of the capacitor provided for the sources of said MOSFETs.
Claim 7
Dependent Claim
229 words
A semiconductor memory system comprising: a plurality of semiconductor memories coupled through a data bus and an address bus; a control circuit coupled to said semiconductor memories through a control bus, wherein each of said semiconductor memories comprises: a memory array including a plurality of word lines, a plurality of data lines and a plurality of memory cells each having a MOSFET and a capacitor; refresh means for outputting a refresh instructing signal for refreshing each of said memory cells; and control signal generating means responsive to said refresh instructing signal for generating a refresh controlling signal, said refresh means including: first refresh signal outputting means for outputting a first refresh timing signal for a predetermined period; a dummy cell having a plurality of MOSFETs and a capacitor which has a capacity smaller than the total capacity of the capacitor provided for the sources of said MOSFETs; a comparator for comparing a voltage held in the capacitor of said dummy cell and a predetermined reference voltage; a second refresh signal outputting means responsive to the output signal of said comparator for outputting a second refresh timing signal when said comparator outputs a signal indicating that the held voltage value of said capacitor is lower than said predetermined reference voltage value; and signal generating means responsive to said first and second refresh timing signals for generating said refresh instructing signal.
Claim 8
Dependent Claim
229 words
A semiconductor memory system comprising: a plurality of semiconductor memories coupled through a data bus and an address bus; a control circuit coupled to said semiconductor memories through a control bus, wherein each of said semiconductor memories comprises: a memory array including a plurality of word lines, a plurality of data lines and a plurality of memory cells each having a MOSFET and a capacitor; refresh means for outputting a refresh instructing signal for refreshing each of said memory cells; and control signal generating means responsive to said refresh instructing signal for generating a refresh controlling signal, said refresh means including: first refresh signal outputting means for outputting a first refresh timing signal for a predetermined period; a dummy cell having a plurality of MOSFETs and a capacitor which has a capacity smaller than the total capacity of the capacitor provided for the sources of said MOSFETs; a comparator for comparing a voltage held in the capacitor of said dummy cell and a predetermined reference voltage; a second refresh signal outputting means responsive to the output signal of said comparator for outputting a second refresh timing signal when said comparator outputs a signal indicating that the held voltage value of said capacitor is lower than said predetermined reference voltage value; and signal generating means responsive to said first and second refresh timing signals for generating said refresh instructing signal.
Claim 9
Dependent Claim
19 words
A semiconductor memory system according to claim 6, wherein said second refresh signal outputting means includes a counter circuit.
Claim 10
Dependent Claim
17 words
A semiconductor memory system according to claim 7, wherein said counter circuit has a plurality of flip-flops.
Claim 11
Dependent Claim
47 words
A semiconductor memory system according to claim 8, wherein said semiconductor memory further comprises: a first address terminal group fed with an address for selecting one of said word lines; and a second address terminal group fed with an address for selecting one of said data lines.
Claim 12
Dependent Claim
35 words
A semiconductor memory system according to claim 6, wherein the capacity of said dummy cell capacitor is smaller by one figure than said total capacity of the capacitor provided for the sources of said MOSFETs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-20 | 1997-06-21 | 1997-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-20 | 2001-06-21 | 2001-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-20 | 2005-06-21 | 2005-12-21 | $7700.00 | Window Closed / Lapsed |