US5272544A
Expired / Lapsed
US
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Digital/analog converter and image processing apparatus using the same
Assignee: Canon Inc
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Filing: 1991-05-23
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Granted: 1993-12-21
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Expires: 2011-05-23
Abstract
Abstract An image processing apparatus having: an unit for receiving a digital multi-value pixel data; a D/A converter for converting the inputted multi-value pixel data into an analog signal; a generator for generating an analog pattern signal synchronously with an input of the digital multi-value pixel data; a sample/hold circuit for sampling and holding the analog signal converted by the D/A converter, synchronously with an input of the digital multi-value pixel data; and a binarizing circuit for generating a binarized pulse signal having a width corresponding to the value of the digital multi-value pixel data by comparing the analog signal held the said sample/hold circuit with the pattern signal generated by the pattern signal generator. A D/A converter having: a digital/analog conversion unit for converting a digital signal into an analog signal at the same speed as the period of generating the digital signal; and a sample/hold circuit for holding and outputting the analog signal converted by the digital/analog conversion unit, synchronously with the period of generating the digital signal.
Inventors
- 👤 Masanori Sakai
- 👤 Kazuhiko Hirooka
- 👤 Masao Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:12
CPC Classifications
H; H04; H04N; H04N1/00; H04N1/40; H04N1/405; H04N1/4055; H04N1/4056
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
125 words
An image processing apparatus comprising: input means for receiving digital multi-value pixel data; converting means for converting the inputted multi-value pixel data into an analog signal; means for generating an analog pattern signal synchronously with an input of the digital multi-value pixel data; sample/hold means for sampling and holding the analog signal converted by said converting means, synchronously with an input of the digital multi-value pixel data; and binarizing means for generating a binarized pulsed signal having a width corresponding to the value of the digital multi-value pixel data by comparing the analog signal held by said sample/hold means with the pattern signal generated by said pattern signal generating means wherein said converting means and said sample/hold means are implemented on a common semiconductor substrate.
Claim 2
Dependent Claim
125 words
An image processing apparatus comprising: input means for receiving digital multi-value pixel data; converting means for converting the inputted multi-value pixel data into an analog signal; means for generating an analog pattern signal synchronously with an input of the digital multi-value pixel data; sample/hold means for sampling and holding the analog signal converted by said converting means, synchronously with an input of the digital multi-value pixel data; and binarizing means for generating a binarized pulsed signal having a width corresponding to the value of the digital multi-value pixel data by comparing the analog signal held by said sample/hold means with the pattern signal generated by said pattern signal generating means wherein said converting means and said sample/hold means are implemented on a common semiconductor substrate.
Claim 3
Dependent Claim
110 words
An image processing apparatus according to claim 1, wherein said pattern signal generating means comprises: clock generating means for generating a clock having a frequency N times as high as that of a clock which is used as a reference clock for an input of said digital multi-value pixel data; means for counting the number of said clocks generated by said clock generating means; a memory for storing a data whose value is related to an address where said data is stored; and second converting means for converting a data produced when the count from said counting means is supplied to said memory as said address, into said analog signal.
Claim 4
Dependent Claim
19 words
An image processing apparatus according to claim 2, wherein said data stored in said memory can be externally changed.
Claim 5
Dependent Claim
52 words
A digital/analog converter according to claim 1, wherein said input means inputs the digital multi-value pixel data in synchronism with a first pixel clock, and wherein said apparatus further comprises means for generating a signal for switching an operational condition of said sample/hold means on the basis of the first pixel clock.
Claim 6
Dependent Claim
38 words
A digital/analog converter according to claim 4, wherein said sample/hold means outputs the analog signal which is delayed by one period of the first pixel clock relative to the digital multi-value pixel data inputted by the input means.
Claim 7
Dependent Claim
92 words
A digital/analog converter comprising: a digital signal input terminal for inputting a digital signal in synchronism with a first clock signal; a digital/analog conversion unit for converting the digital signal inputted from said digital signal input terminal into an analog signal; and a sample/hold circuit for holding and outputting the analog signal converted by said digital/analog conversion unit, synchronously with a second clock signal having the same frequency as the frequency of the first clock signal; wherein said digital/analog conversion unit and said sample/hold circuit are implemented on a common semiconductor substrate.
Claim 8
Dependent Claim
92 words
A digital/analog converter comprising: a digital signal input terminal for inputting a digital signal in synchronism with a first clock signal; a digital/analog conversion unit for converting the digital signal inputted from said digital signal input terminal into an analog signal; and a sample/hold circuit for holding and outputting the analog signal converted by said digital/analog conversion unit, synchronously with a second clock signal having the same frequency as the frequency of the first clock signal; wherein said digital/analog conversion unit and said sample/hold circuit are implemented on a common semiconductor substrate.
Claim 9
Dependent Claim
49 words
A digital/analog converter according to claim 6, further comprising: a first clock signal input terminal for inputting the first clock signal; and second clock signal generating means for generating the second clock signal on the basis of the first clock signal inputted from said first clock signal input terminal.
Claim 10
Dependent Claim
33 words
A digital/analog converter according to claim 6, wherein said digital/analog conversion unit outputs an analog signal which is delayed by one period of the first clock signal relative to the inputted digital signal.
Claim 11
Dependent Claim
143 words
An image processing apparatus comprising: input means for inputting digital multi-value pixel data in synchronism with a first pixel clock signal; converting means for converting the inputted multi-value pixel data into an analog signal; means for generating an analog pattern signal synchronously with the first pixel clock signal; sample/hold means for sampling the analog signal converted by said converting means and holding the converted analog signal during substantially one period of the first pixel clock signal, said sample/hold means operating synchronously with a second pixel clock signal having the same frequency as a frequency of the first pixel clock signal; and binarizing means for generating a binarized pulse signal having a width corresponding to the value of the digital multi-value pixel data by comparing the analog signal held by said sample/hold means with the pattern signal generated by said pattern signal generating means.
Claim 12
Dependent Claim
143 words
An image processing apparatus comprising: input means for inputting digital multi-value pixel data in synchronism with a first pixel clock signal; converting means for converting the inputted multi-value pixel data into an analog signal; means for generating an analog pattern signal synchronously with the first pixel clock signal; sample/hold means for sampling the analog signal converted by said converting means and holding the converted analog signal during substantially one period of the first pixel clock signal, said sample/hold means operating synchronously with a second pixel clock signal having the same frequency as a frequency of the first pixel clock signal; and binarizing means for generating a binarized pulse signal having a width corresponding to the value of the digital multi-value pixel data by comparing the analog signal held by said sample/hold means with the pattern signal generated by said pattern signal generating means.
Claim 13
Dependent Claim
39 words
An image processing apparatus according to claim 9, wherein said sample/hold means outputs an analog signal which is delayed by one period of the first clock signal relative to the digital multi-value pixel data inputted by the input means.
References Cited (Backward Citations)
US4926248A
Cited
US4800442A
Cited
US4811037A
Cited
US4819066A
Cited
US5029227A
Cited
US4926268A
Cited
US4868684A
Cited
US4864305A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-20 | 1997-06-21 | 1997-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-20 | 2001-06-21 | 2001-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-20 | 2005-06-21 | 2005-12-21 | $7700.00 | Window Closed / Lapsed |