US5271004A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asynchronous transfer mode switching arrangement providing broadcast transmission
Assignee: GPT Ltd
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Filing: 1991-08-27
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Granted: 1993-12-14
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Expires: 2011-08-27
Abstract
Abstract An asynchronous transfer mode switching arrangement includes a serial to parallel converter arranged to receive input packets of data, which include routing information, in serial form and convert the packets of data to parallel form. A first random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the first random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output. The first random access memory and the output queues are controlled by a memory management arrangement to which is connected a broadcast channel routine second random access memory. The memory management arrangement addresses the broadcast channel routine second random access memory with channel index information, and receives information identifying the required output ports.
Inventors
- 👤 Richard J. Proctor
- 👤 Thomas S. Maddern
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:24
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L12/02; H04L12/16; H04L12/18; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/108; H04L49/20; H04L49/201; H04L49/203; H04L49/30; H04L49/3081; H04L49/309; H04L2012/5678; H04L2012/5681
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
199 words
An asynchronous transfer mode switching arrangement, comprising: a serial to parallel converter having inputs to receive input packets of data which include routing information, in serial form, and convert the input packets of data to parallel form, said serial to parallel converter being connected to a first random access memory in which each input packet of data is entered at an address location in the first random access memory, and the address is then entered in a respective first-in and first-out output queue at the tail, and the address at the head of the queue is accessed, and the packet of data is read from the first random access memory into a parallel to serial converter connected thereto, and the packet of data is serially delivered to a required output of the parallel to serial converter, wherein the first random access memory and the output queues are controlled by a memory management arrangement connected thereto, said memory management arrangement being further connected to a second random access memory containing broadcast channel routines which is arranged to receive channel index information from the memory management arrangement and generate information identifying required output ports to which information is to be broadcast.
Claim 2
Dependent Claim
199 words
An asynchronous transfer mode switching arrangement, comprising: a serial to parallel converter having inputs to receive input packets of data which include routing information, in serial form, and convert the input packets of data to parallel form, said serial to parallel converter being connected to a first random access memory in which each input packet of data is entered at an address location in the first random access memory, and the address is then entered in a respective first-in and first-out output queue at the tail, and the address at the head of the queue is accessed, and the packet of data is read from the first random access memory into a parallel to serial converter connected thereto, and the packet of data is serially delivered to a required output of the parallel to serial converter, wherein the first random access memory and the output queues are controlled by a memory management arrangement connected thereto, said memory management arrangement being further connected to a second random access memory containing broadcast channel routines which is arranged to receive channel index information from the memory management arrangement and generate information identifying required output ports to which information is to be broadcast.
Claim 3
Dependent Claim
57 words
An asynchronous transfer mode switching arrangement as claimed in claim 1, wherein the routing information forming a part of each input packet of data comprises a section identifying a classification dependent field and a section identifying a cell type, wherein the cell type section is used to identify that the packet of data is a broadcast cell.
Claim 4
Dependent Claim
60 words
An asynchronous transfer mode switching arrangement as claimed in claim 2, wherein the classification dependent field comprises a plurality of index bits and a parity bit, wherein the plurality of index bits are used to address a location within the first random access memory which defines an address of a required output port contained within the first random access memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |