US5268877A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital beamforming and filtering circuit
Assignee: NAVY United States, AS REPRSENTED BY SECRETARY OF
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Filing: 1992-05-11
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Granted: 1993-12-07
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Expires: 2012-05-11
Abstract
Abstract A beamformer system is disclosed which includes an array of sensors such asydrophones which produce signals from which information relating to a target is to be determined. The beamformer system includes a channel for each sensor, the channel including a varable length shift register which provides bulk delay to received signals, a FIR interpolation filter which provides vernier delay and shading. The system also includes a summation tree which adds the received signals and a sign extension/bit reversal filter to avoid authmetic overflow.
Inventors
- 👤 Douglas L. Odell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:56
CPC Classifications
G; G10; G10K; G10K11/00; G10K11/18; G10K11/26; G10K11/34; G10K11/341; G10K11/346; G01; G01S; G01S3/00; G01S3/80; G01S3/802; G01S3/808; G01S3/8083
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
85 words
A circuit for enhancing the amplitude of a signal received by the circuit relative to ambient noise and directional interference comprising; first means for providing a predetermined bulk delay to the signal received by the circuit, second means including a sign extension/bit reversal filter for filtering signal data words received from the first means and, third means for providing a predetermined vernier delay to the signal received from the second means, whereby a signal indicating the amplitude of the signal received by the is generated.
Claim 2
Dependent Claim
85 words
A circuit for enhancing the amplitude of a signal received by the circuit relative to ambient noise and directional interference comprising; first means for providing a predetermined bulk delay to the signal received by the circuit, second means including a sign extension/bit reversal filter for filtering signal data words received from the first means and, third means for providing a predetermined vernier delay to the signal received from the second means, whereby a signal indicating the amplitude of the signal received by the is generated.
Claim 3
Dependent Claim
18 words
A circuit as set forth in claim 1 wherein the first means includes a variable length shift register.
Claim 4
Dependent Claim
21 words
A circuit as set forth in claim 1 and further including a summation tree which acts to sum the received signals.
Claim 5
Dependent Claim
17 words
A circuit as set forth in claim 1 wherein the third means includes a FIR interpolation filter.
Claim 6
Dependent Claim
85 words
A circuit for enhancing the amplitude of a signal received by the circuit relative to ambient noise and directional interference comprising; first means for providing a predetermined bulk delay to the signal received by the circuit, second means for filtering signal data words received from the first means and, third means including a FIR interpolation filter for providing a predetermined vernier delay to the signal received from the second means, whereby a signal indicating the amplitude of the signal received by the circuit is generated.
Claim 7
Dependent Claim
85 words
A circuit for enhancing the amplitude of a signal received by the circuit relative to ambient noise and directional interference comprising; first means for providing a predetermined bulk delay to the signal received by the circuit, second means for filtering signal data words received from the first means and, third means including a FIR interpolation filter for providing a predetermined vernier delay to the signal received from the second means, whereby a signal indicating the amplitude of the signal received by the circuit is generated.
Claim 8
Dependent Claim
18 words
A circuit as set forth in claim 5 wherein the second means includes a sign extension/bit reversal filter.
Claim 9
Dependent Claim
18 words
A circuit as set forth in claim 5 wherein the first means includes a variable length shift register.
Claim 10
Dependent Claim
21 words
A circuit as set forth in claim 5 and further including a summation tree which acts to sum the received signals.
References Cited (Backward Citations)
US4207620A
Cited
US5014712A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |