Infrared focal plane array processor with integration and low pass filter per pixel

Claim 2

A focal plane array circuit member comprising: (a) a pixel of predetermined area providing a charge in response to impingement of radiation thereon; (b) a charge storing circuit for storing said charge responsive to reception of said radiations by said pixel; (c) switch means for periodically transferring charge from said charge storing circuit and then discharging said charge storing circuit; (d) storage means for storing said transferred charge; (e) an output terminal; and (f) a low pass filter coupled between said output terminal and said storage means, (g) said structure of (b) through (f) displacing an area in a single semiconductor chip substantially the same as the area of said pixel.

Claim 3

A circuit as set forth in claim 1 wherein said charge storing circuit comprises a focal plane array detector element including a capacitor for storing charge.

Claim 4

A circuit as set forth in claim 1 wherein said switch means includes a transistor coupling said charge storing circuit to a source of reference voltage and a transistor coupling said charge storing circuit to said storage means.

Claim 5

A circuit as set forth in claim 2 wherein said switch means includes a transistor coupling said charge storing circuit to a source of reference voltage and a transistor coupling said charge storing circuit to said storage means.

Claim 6

A circuit as set forth in claim 1 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 7

A circuit as set forth in claim 2 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 8

A circuit as set forth in claim 3 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 9

A circuit as set forth in claim 4 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 10

A focal plane array circuit comprising: (a) a plurality of charge storing circuits arranged in a matrix, each said charge storing circuit including a pixel of predetermined area, storing a charge responsive to reception of infrared radiations on said pixels; each said charge storing circuit further including: (b) switch means for periodically transferring charge from said charge storing circuit and then discharging said charge storing circuit; (c) storage means for storing said transferred charge; (d) an output terminal; and (e) a low pass filter coupled between said output terminal and said storage means; (f) said structure of (a) through (e) excluding said pixel displacing an area in a single semiconductor chip substantially the same as the area of said pixel.

Claim 11

A focal plane array circuit comprising: (a) a plurality of charge storing circuits arranged in a matrix, each said charge storing circuit including a pixel of predetermined area, storing a charge responsive to reception of infrared radiations on said pixels; each said charge storing circuit further including: (b) switch means for periodically transferring charge from said charge storing circuit and then discharging said charge storing circuit; (c) storage means for storing said transferred charge; (d) an output terminal; and (e) a low pass filter coupled between said output terminal and said storage means; (f) said structure of (a) through (e) excluding said pixel displacing an area in a single semiconductor chip substantially the same as the area of said pixel.

Claim 12

A circuit as set forth in claim 1 wherein said charge storing circuits each comprise a focal plane array detector element including a capacitor for storing charge.

Claim 13

A circuit as set forth in claim 1 wherein said switch means includes a transistor coupling said charge storing circuit to a source of reference voltage and a transistor coupling said charge storing circuit to said storage means.

Claim 14

A circuit as set forth in claim 10 wherein said switch means includes a transistor coupling said charge storing circuit to a source of reference voltage and a transistor coupling said charge storing circuit to said storage means.

Claim 15

A circuit as set forth in claim 9 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 16

A circuit as set forth in claim 10 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 17

A circuit as set forth in claim 11 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 18

A circuit as set forth in claim 12 wherein said low pass filter comprises a resistor having a resistance on the order of 10 9 ohms disposed between said storage means and said output terminal and a capacitor having a capacitance on the order of 10 -12 to 10 -13 farads coupled between said output terminal and said source of reference voltage.

Claim 21

A method as set forth in claim 17 wherein said storage device comprises a focal plane array detector element including a capacitor for storing charge.

Claim 22

A method as set forth in claim 17 wherein said switch means includes a transistor coupling said charge storing circuit to a source of reference voltage and a transistor coupling said charge storing circuit to said storage means.

Claim 23

A method as set forth in claim 18 wherein said switch means includes a transistor coupling said charge storing circuit to a source of reference voltage and a transistor coupling said charge storing circuit to said storage means.