US5265048A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor storage device and method of accessing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1991-01-14
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Granted: 1993-11-23
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Expires: 2011-01-14
Abstract
Abstract The storage area of a memory cell array is divided into a main area and auxiliary areas. The main area has a large storage capacity as compared with the auxiliary areas, and stores ordinary processed data and the like. The auxiliary areas store any desired identification data. The address spaces of the main area and auxiliary areas overlap each other. That is, the access to the auxiliary areas is effected by using part of the address inputs used for addressing the main area. Area switching means allows the use of time sharing for the memory cell array by switching accessible storage areas between the main area and auxiliary areas.
Inventors
- 👤 Masatoshi Kimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:37
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
87 words
A semiconductor storage device comprising: a memory cell array with a single storage area composed of a plurality of regularly arranged memory cells, said storage area being divided into a main area of relatively large storage capacity and auxiliary areas of relatively small storage capacity, said main area being accessible through first address inputs, said auxiliary areas being accessible through second address inputs which are part of said first address inputs, and an area switching circuit for selective switching between said main area and said auxiliary areas.
Claim 2
Dependent Claim
87 words
A semiconductor storage device comprising: a memory cell array with a single storage area composed of a plurality of regularly arranged memory cells, said storage area being divided into a main area of relatively large storage capacity and auxiliary areas of relatively small storage capacity, said main area being accessible through first address inputs, said auxiliary areas being accessible through second address inputs which are part of said first address inputs, and an area switching circuit for selective switching between said main area and said auxiliary areas.
Claim 3
Dependent Claim
28 words
A semiconductor storage device as set forth in claim 1, wherein: said area switching circuit executes the switching a predetermined time after the turning-on of said the power.
Claim 4
Dependent Claim
47 words
A semiconductor storage device as set forth in claim 2, wherein: said area switching circuit includes timer means for detecting the passage of a predetermined time after the turning-on of the power, the switching storage are being executed in response to the output from said timer means.
Claim 5
Dependent Claim
36 words
A semiconductor storage device as set forth in claim 1, wherein: said area switching circuit executes the switching of said in response to a signal given from outside the semiconductor chip on which it is mounted.
Claim 6
Dependent Claim
35 words
A semiconductor storage device as set forth in claim 4, wherein; the signal given from outside the semiconductor chip is an exclusive switching control signal for giving a command for said switching of accessible areas.
Claim 7
Dependent Claim
64 words
A semiconductor storage device as set forth in claim 4, wherein the signal given from outside the semiconductor chip is a group of control signals for controlling the timing for the writing of data into and reading of data from said memory cell array, and said area switching circuit executes the switching said when said group of control signals have a predetermined logical combination.
Claim 8
Dependent Claim
72 words
A semiconductor storage device as set forth in claim 1, including: first address designating means for designating the address of a first fixed length of said main area by said first address inputs, and second address designating means for designating the address of a second fixed length of said auxiliary areas by said second address inputs, said area switching circuit including means for selectively activating said first and second address designating means.
Claim 9
Independent Claim
90 words
A method of accessing a semiconductor storage device, comprising the steps of: dividing a single storage area of a memory cell array composed of a plurality of regularly arranged memory cells, into a main area of relatively large storage capacity and auxiliary areas of relatively small storage capacity, and accessing said main area by using first address data, accessing said auxiliary areas by using second address data which are part of said first address data, wherein said accessing is effected by switching between said main area and said auxiliary areas.
Claim 10
Independent Claim
90 words
A method of accessing a semiconductor storage device, comprising the steps of: dividing a single storage area of a memory cell array composed of a plurality of regularly arranged memory cells, into a main area of relatively large storage capacity and auxiliary areas of relatively small storage capacity, and accessing said main area by using first address data, accessing said auxiliary areas by using second address data which are part of said first address data, wherein said accessing is effected by switching between said main area and said auxiliary areas.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |