US5264847A
Expired / Lapsed
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Data decoder
Assignee: Sony United Kingdom Ltd
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Filing: 1992-08-06
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Granted: 1993-11-23
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Expires: 2012-08-06
Abstract
Abstract A data decoder is described for decoding interleaved first type code words [RUNLENGTH, SIZE] and second type code words [AMPLITUDE], each first type code word serving to define a runlength of constant values preceding a variable value defined by a following second type code word. The first type code words and the second type code words are fed to respective first and second pipeline delay units 22 and 24. The output from the first pipeline delay unit 22 is fed to a state machine 26 which reads the RUNLENGTH value and generates an INSERT ZEROS signal for a period proportional to the RUNLENGTH value followed by a signal triggering reading of the second pipeline delay unit 24. The INSERT ZEROS signal and the output of the second pipeline delay unit 24 are fed to a multiplexer 28 which selects between them to generate the appropriate OUTPUT signal. A swing buffer 10 is disposed upstream of the first and second pipeline delay units 22 and 24. The second pipeline delay unit 24 is also used to effect fixed length code decoding.
Inventors
- 👤 Rajan Bhandari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:29
CPC Classifications
H; H04; H04N; H04N19/00; H03; H03M; H03M7/00; H03M7/30; H03M7/46; H04N19/60; H04N19/90; H04N19/93; H04N19/10; H04N19/102; H04N19/13; H04N19/91
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A data decoder for decoding interleaved first type code words and second type code words, each said first type code word serving to define a runlength of constant values preceding a variable value defined by a following second type code word, said data decoder comprising: (i) a first pipeline delay unit for buffering said first type code words; (ii) a second pipeline delay unit for buffering said second type code words; (iii) a multiplexer for selectively outputting values generated from code words within said first pipeline delay unit and from code words within said second pipeline delay unit; and (iv) a state machine responsive to a first type code word read from said first pipeline delay unit for generating a run of constant values as defined by said first type code word for output via said multiplexer followed by a signal for switching said multiplexer to read a variable value defined by a second type code word from said second pipeline delay unit.
Claim 2
Dependent Claim
163 words
A data decoder for decoding interleaved first type code words and second type code words, each said first type code word serving to define a runlength of constant values preceding a variable value defined by a following second type code word, said data decoder comprising: (i) a first pipeline delay unit for buffering said first type code words; (ii) a second pipeline delay unit for buffering said second type code words; (iii) a multiplexer for selectively outputting values generated from code words within said first pipeline delay unit and from code words within said second pipeline delay unit; and (iv) a state machine responsive to a first type code word read from said first pipeline delay unit for generating a run of constant values as defined by said first type code word for output via said multiplexer followed by a signal for switching said multiplexer to read a variable value defined by a second type code word from said second pipeline delay unit.
Claim 3
Dependent Claim
62 words
A data decoder as claimed in claim 1, further comprising a swing buffer for buffering fields of data composed of a plurality of first type code words and a plurality of second type code words prior to passing said first type code words and said second type code words to said first pipeline delay unit and said second pipeline delay unit respectively.
Claim 4
Dependent Claim
38 words
A data decoder as claimed in claim 1, wherein said second pipeline delay unit also performs a decoding operation on said second type code words as said second type code words pass through said second pipeline delay unit.
Claim 5
Dependent Claim
53 words
A data decoder as claimed in claim 3, wherein each said first type code word also defines the bit length of a following second type code word, and wherein a signal indicative of said bit length is fed to said second pipeline delay unit for use in decoding said second type code words.
Claim 6
Dependent Claim
20 words
A data decoder as claimed in claim 3, wherein said second pipeline delay unit is a fixed length code decoder.
Claim 7
Dependent Claim
20 words
A data decoder as claimed in claim 1, wherein said constant values are zeros and said variable values are non-zeros.
Claim 8
Dependent Claim
14 words
An image data decompression apparatus including a data decoder as claimed in claim 1.
Claim 9
Dependent Claim
160 words
A data decoding method for decoding interleaved first type code words and second type code words, each said first type code word serving to define a runlength of constant values preceding a variable value defined by a following second type code word, said data decoding method comprising the steps of: (i) buffering said first type code words in a first pipeline delay unit; (ii) buffering said second type code words in a second pipeline delay unit; (iii) reading with a state machine a first type code word from said first pipeline delay unit; (iv) generating with said state machine a run of constant values defined by said first type code word for output via a multiplexer followed by a signal for switching said multiplexer to read a variable value defined by a second type code word from said second pipeline delay unit for output via said multiplexer; and (v) outputting said constant values and said variable value via said multiplexer.
Claim 10
Dependent Claim
160 words
A data decoding method for decoding interleaved first type code words and second type code words, each said first type code word serving to define a runlength of constant values preceding a variable value defined by a following second type code word, said data decoding method comprising the steps of: (i) buffering said first type code words in a first pipeline delay unit; (ii) buffering said second type code words in a second pipeline delay unit; (iii) reading with a state machine a first type code word from said first pipeline delay unit; (iv) generating with said state machine a run of constant values defined by said first type code word for output via a multiplexer followed by a signal for switching said multiplexer to read a variable value defined by a second type code word from said second pipeline delay unit for output via said multiplexer; and (v) outputting said constant values and said variable value via said multiplexer.
References Cited (Backward Citations)
US5181031A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |