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US5264784A Expired / Lapsed US ⏱️ 0.0 years remaining

Current mirror with enable

Assignee: NXP USA Inc
•
Filing: 1992-06-29
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Granted: 1993-11-23
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Expires: 2012-06-29
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Abstract

Abstract A current mirror circuit that can be disabled has been provided. An enable signal is applied to the base of a transistor that drives the common bases of an emitter-coupled pair of transistors. A voltage level of the enable signal may be used to turn off the transistor which subsequently turns off and disables the emitter-coupled pair of transistors.

Inventors

  • 👤 Jeffery P. Ortiz

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 21:51
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 218 words
A current mirror circuit responsive to an enable signal, comprising: an emitter-coupled pair of transistors including a first and a second transistor each having a collector, a base and an emitter, said emitters of said first and second transistors being coupled to a first supply voltage terminal, said collector of said second transistor providing an output current of the current mirror circuit; a third transistor having a collector, a base and an emitter, said collector of said third transistor being coupled to a second supply voltage terminal, said emitter of said third transistor being coupled to said base of said first transistor; a first resistor being coupled between said collector of said first transistor and said second supply voltage terminal; and enable means responsive to the enable signal and being coupled to said collector of said first transistor and said base of said third transistor for maintaining a voltage appearing at the collector of said first transistor substantially equal to a voltage appearing at the base of said first transistor when the enable signal exceeds a predetermined threshold thereby allowing a current flowing through said first transistor to be substantially independent of the enable signal and for turning off said third transistor and subsequently disabling the current mirror circuit when the enable signal falls below a predetermined threshold.
Claim 2
Dependent Claim 218 words
A current mirror circuit responsive to an enable signal, comprising: an emitter-coupled pair of transistors including a first and a second transistor each having a collector, a base and an emitter, said emitters of said first and second transistors being coupled to a first supply voltage terminal, said collector of said second transistor providing an output current of the current mirror circuit; a third transistor having a collector, a base and an emitter, said collector of said third transistor being coupled to a second supply voltage terminal, said emitter of said third transistor being coupled to said base of said first transistor; a first resistor being coupled between said collector of said first transistor and said second supply voltage terminal; and enable means responsive to the enable signal and being coupled to said collector of said first transistor and said base of said third transistor for maintaining a voltage appearing at the collector of said first transistor substantially equal to a voltage appearing at the base of said first transistor when the enable signal exceeds a predetermined threshold thereby allowing a current flowing through said first transistor to be substantially independent of the enable signal and for turning off said third transistor and subsequently disabling the current mirror circuit when the enable signal falls below a predetermined threshold.
Claim 3
Dependent Claim 73 words
The current mirror circuit according to claim 1 wherein said enable means includes: a diode having an anode and a cathode, said cathode of said diode being coupled to said collector of said first transistor, said anode of said diode being coupled to said base of said third transistor; and a second resistor being coupled between said base of said third transistor and a first terminal at which the enable signal is applied.
Claim 4
Dependent Claim 221 words
A current mirror circuit with enable comprising: a first transistor having a collector, a base and an emitter, said emitter of said first transistor being coupled to a first supply voltage terminal; a second transistor having a collector, a base and an emitter, said emitter of said second transistor being coupled to said first supply voltage terminal, said base of said second transistor being coupled to said base of said first transistor, and said collector of said second transistor providing an output current of the current mirror circuit; a third transistor having a collector, a base and an emitter, said collector of said third transistor being coupled to a second supply voltage terminal, said emitter of said third transistor being coupled to said base of said first transistor; a diode having an anode and a cathode, said cathode of said diode being coupled to said collector of said first transistor, said anode of said diode being coupled to said base of said third transistor; a first resistor being coupled between said collector of said first transistor and said second supply voltage terminal; and a second resistor being coupled between said base of said third transistor and a first terminal at which an enable signal is applied, wherein a current flowing through said first transistor is substantially independent of the enable signal.
Claim 5
Dependent Claim 221 words
A current mirror circuit with enable comprising: a first transistor having a collector, a base and an emitter, said emitter of said first transistor being coupled to a first supply voltage terminal; a second transistor having a collector, a base and an emitter, said emitter of said second transistor being coupled to said first supply voltage terminal, said base of said second transistor being coupled to said base of said first transistor, and said collector of said second transistor providing an output current of the current mirror circuit; a third transistor having a collector, a base and an emitter, said collector of said third transistor being coupled to a second supply voltage terminal, said emitter of said third transistor being coupled to said base of said first transistor; a diode having an anode and a cathode, said cathode of said diode being coupled to said collector of said first transistor, said anode of said diode being coupled to said base of said third transistor; a first resistor being coupled between said collector of said first transistor and said second supply voltage terminal; and a second resistor being coupled between said base of said third transistor and a first terminal at which an enable signal is applied, wherein a current flowing through said first transistor is substantially independent of the enable signal.
Claim 6
Dependent Claim 221 words
A current mirror circuit with enable, comprising: a first transistor having a collector, a base and an emitter, said emitter of said first transistor being coupled to a first supply voltage terminal; a second transistor having a collector, a base and an emitter, said emitter of said second transistor being coupled to said first supply voltage terminal, said base of said second transistor being coupled to said base of said first transistor, and said collector of said second transistor providing an output current of the current mirror circuit; a third transistor having a collector, a base and an emitter, said collector of said third transistor being coupled to a second supply voltage terminal, said emitter of said third transistor being coupled to said base of said first transistor; a diode having an anode and a cathode, said anode of said diode being coupled to said collector of said first transistor, said cathode of said diode being coupled to said base of said third transistor; a first resistor being coupled between said collector of said first transistor and said second supply voltage terminal; and a second resistor being coupled between said base of said third transistor and a first terminal at which an enable signal is applied, wherein a current flowing through said first transistor is substantially independent of the enable signal.
Claim 7
Dependent Claim 221 words
A current mirror circuit with enable, comprising: a first transistor having a collector, a base and an emitter, said emitter of said first transistor being coupled to a first supply voltage terminal; a second transistor having a collector, a base and an emitter, said emitter of said second transistor being coupled to said first supply voltage terminal, said base of said second transistor being coupled to said base of said first transistor, and said collector of said second transistor providing an output current of the current mirror circuit; a third transistor having a collector, a base and an emitter, said collector of said third transistor being coupled to a second supply voltage terminal, said emitter of said third transistor being coupled to said base of said first transistor; a diode having an anode and a cathode, said anode of said diode being coupled to said collector of said first transistor, said cathode of said diode being coupled to said base of said third transistor; a first resistor being coupled between said collector of said first transistor and said second supply voltage terminal; and a second resistor being coupled between said base of said third transistor and a first terminal at which an enable signal is applied, wherein a current flowing through said first transistor is substantially independent of the enable signal.

References Cited (Backward Citations)

US4370674A Cited
US4612496A Cited
US4595972A Cited
US4786856A Cited
US5013934A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-11-22 1997-05-24 1997-11-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-11-22 2001-05-24 2001-11-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-11-22 2005-05-24 2005-11-23 $7700.00 Window Closed / Lapsed

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