US5263002A
Expired / Lapsed
US
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Semiconductor memory device and its topography
Assignee: KABUSHIKI KASIAH TOSIBA H
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Filing: 1991-06-12
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Granted: 1993-11-16
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Expires: 2011-06-12
Abstract
Abstract In the semiconductor memory device, memory cells are divided into plural blocks; each block is further divided into plural I/O unit groups; and furthermore each I/O unit group is divided into plural small groups. The word lines provided for each small group of memory cells arranged at similar locations in each unit group are connected in common to a word line selecting line selected by a select circuit. Therefore, the number of memory cells connected to one word line can be reduced to decrease the power consumption and to increase the operating speed, without increasing the wiring capacitance and the chip size.
Inventors
- 👤 Youichi Suzuki
- 👤 Makoto Segawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C8/00; G11C8/14; G11C7/00; G11C7/10
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
166 words
A semiconductor memory device, comprising: a memory cell array composed of memory cells arranged in matrix fashion and divided into a plurality of blocks, memory cells in each of said divided blocks being further divided into a plurality of input/output unit groups and each of said divided units groups being further divided into a plurality of small groups each composed of the same number of memory cells; a plurality of word lines provided for each of said small groups; a plurality of word line selecting lines connected in common to word lines connected to a small group of memory cells arranged at similarly corresponding locations in each of said divided unit groups; and a select circuit for selecting any one of said plurality of word line selecting lines; and wherein said select circuit is separately provided on both side portions of each of said blocks so as to be connected to the word line selecting lines extending from both side portions of each of the blocks.
Claim 2
Dependent Claim
166 words
A semiconductor memory device, comprising: a memory cell array composed of memory cells arranged in matrix fashion and divided into a plurality of blocks, memory cells in each of said divided blocks being further divided into a plurality of input/output unit groups and each of said divided units groups being further divided into a plurality of small groups each composed of the same number of memory cells; a plurality of word lines provided for each of said small groups; a plurality of word line selecting lines connected in common to word lines connected to a small group of memory cells arranged at similarly corresponding locations in each of said divided unit groups; and a select circuit for selecting any one of said plurality of word line selecting lines; and wherein said select circuit is separately provided on both side portions of each of said blocks so as to be connected to the word line selecting lines extending from both side portions of each of the blocks.
Claim 3
Dependent Claim
21 words
The semiconductor memory device according to claim 1, wherein a sense amplifier is provided for each of said divided unit groups.
Claim 4
Dependent Claim
31 words
The semiconductor memory device according to claim 1 wherein said word line selecting lines belonging to a common single row are connected to a row select line via said select circuit.
Claim 5
Dependent Claim
31 words
The semiconductor memory device according to claim 1, wherein said word line selecting lines belonging to a plurality of rows are connected to a row select line via said select circuit.
Claim 6
Dependent Claim
42 words
The semiconductor memory device according to claim 1, wherein memory cells connected to said word line selecting lines connected to the same row select line so as to form one input/output unit group in different rows are connected to a common amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-15 | 1997-05-17 | 1997-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-15 | 2001-05-17 | 2001-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-15 | 2005-05-17 | 2005-11-16 | $7700.00 | Window Closed / Lapsed |