IC device for drive control of small hard disk drive unit

Claim 2

A drive control circuit for controlling the spindle motor of a small hard disk drive (HDD) unit, comprising: a first voltage detecting circuit for generating a first detection signal for controlling the operation of the spindle motor of the small HDD unit in response to the voltage of a first terminal connected to a power source for driving the motor; a second voltage detecting circuit for generating a second detection signal for controlling the operation of said motor in response to the voltage of a second terminal connected to another power source for driving a control circuit to control said motor; and control signal generating means for keeping valid said first detection signal during a period from the time the voltage at said first terminal surpasses a prescribed level higher than the upper limit of the prescribed voltage range of the power source for driving the control circuit until the time said voltage reaches another prescribed value lower than the lower limit of the prescribed voltage range, and supplying said control circuit with the logical sum of the valid first detection signal and said second detection signal.

Claim 3

A drive control circuit, as claimed in claim 1, wherein said first voltage detecting circuit consists of a circuit for generating said first detection signal which takes on an active level when the voltage at said first terminal is below a first reference voltage of a prescribed level; said second voltage detecting circuit consists of a circuit for generating said second detection signal which takes on an active level when the voltage at said second terminal is below a second reference voltage which is below the lower limit of the prescribed voltage range of said control circuit driving power source; and said control signal generating means is provided with means for generating a third detection signal which takes on an active level when the voltage at said first terminal is lower than a third reference voltage which is between the upper limit of the prescribed voltage range of said control circuit driving power source and said first reference voltage, means for generating a fourth detection signal VD4 which takes on an active level when the voltage at said second terminal is lower than a fourth reference voltage which is between the lower limit of the prescribed voltage range of said control circuit driving power source and said second reference voltage, and a logic circuit responsive to said first, third and fourth detection signals for keeping said first detection signal valid from the time the voltage at said first terminal surpasses said third reference voltage until it falls to said fourth reference voltage and supplying the logical sum of this valid first detection signal and said second detection signal to said control circuit.

Claim 4

A drive control circuit, as claimed in claim 2, wherein the normal voltage at said first terminal is set at 12 V; said first reference voltage; at about 10 V; the center value of said prescribed voltage range of said control circuit power source, at 5 V; said second reference voltage, at about 4 V; said third reference voltage, at about 8 V; and said fourth reference voltage; at about 3 V.

Claim 5

A drive control circuit, as claimed in claim 2, wherein the normal voltage at said first terminal is set at 24 V; said first reference voltage, at about 20 V; and said third reference voltage, at about 17 V.

Claim 6

A drive control circuit, as claimed in claim 2, wherein said logic circuit comprises: a first inverter circuit for inverting the level of said first detection signal, a second inverter circuit for inverting the level of said third detection signal, a plurality of third inverter circuits connected in cascade to each other so as to invert the level of said fourth detection signal, a NOR gate receiving with a pair of input terminals said fourth detection signal and the output signal of said first inverter circuit; a fourth inverter circuit for inverting the level of the output signal of said NOR gate, a flip-flop circuit receiving the supply of the output signal of said second inverter circuit at its data input terminal, the supply of the output signal of said fourth inverter circuit at its clock input terminal, and the supply of the output signal of said third inverter circuit at its reset input terminal, a first OR gate circuit receiving with a pair of input terminals the output signal of said flip-flop circuit and the output signal of said second inverter circuit; an AND gate circuit receiving the supply of the output signal of said first OR gate circuit and of said first detection signal; and a second OR gate circuit receiving the supply of the output signal of said AND gate circuit and of said second detection signal.