US5261281A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ultrasonic imaging apparatus
Assignee: Hitachi Healthcare Manufacturing Ltd
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Filing: 1992-11-12
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Granted: 1993-11-16
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Expires: 2012-11-12
Abstract
Abstract A phase adjustment circuit for use in an ultrasonic apparatus which respectively time-adjusts a plurality of received signals from an ultrasonic transducer array and sets wave fronts of the reflected waves from particular positions into an in-phase state and adds the in-phase signals, thereby obtaining a received beam. The received signals are mixed with phase-controlled reference signals. The low frequency component of the mixed wave is sequentially sampled and stored in a memory which is controlled by a clock signal of a predetermined period, and thereafter, the stored sampled signals are read out. Most of the necessary time adjustment results from the difference between the writing time and the reading time. The remaining micro time adjustment is performed by phase control of the reference signals.
Inventors
- 👤 Kageyoshi Katakura
- 👤 Shin-ichi Kondo
- 👤 Hiroshi Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:28
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/52; G01S7/52017; G01S7/52046
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
190 words
Apparatus for processing signals from a plurality of ultrasonic transducer elements resulting from ultrasonic waves received by the transducer elements, said apparatus comprising: a plurality of reception channels, each reception channel including a mixer for mixing a signal from a respective ultrasonic transducer element with a time-controlled reference signal, a filter for filtering the mixed signals to produce a low frequency output, and a sampling and memory circuit for periodically sampling the filter output and storing the sampled filter output and for periodically reading out the stored filter output; control means for providing write addresses and read addresses for the plurality of sampling and memory circuits to cause an addressed sampling and memory circuit to sample and store filter output, with a uniquely selected delay time between storing and reading out by any one of the sampling and memory circuits, said control means further providing reference signals to the plurality of mixers, the reference signal for a respective mixer being dependent upon the selected delay time for that mixer; and adding means for adding the read outputs from the plurality of sampling and memory circuits to provide a received signal.
Claim 2
Dependent Claim
190 words
Apparatus for processing signals from a plurality of ultrasonic transducer elements resulting from ultrasonic waves received by the transducer elements, said apparatus comprising: a plurality of reception channels, each reception channel including a mixer for mixing a signal from a respective ultrasonic transducer element with a time-controlled reference signal, a filter for filtering the mixed signals to produce a low frequency output, and a sampling and memory circuit for periodically sampling the filter output and storing the sampled filter output and for periodically reading out the stored filter output; control means for providing write addresses and read addresses for the plurality of sampling and memory circuits to cause an addressed sampling and memory circuit to sample and store filter output, with a uniquely selected delay time between storing and reading out by any one of the sampling and memory circuits, said control means further providing reference signals to the plurality of mixers, the reference signal for a respective mixer being dependent upon the selected delay time for that mixer; and adding means for adding the read outputs from the plurality of sampling and memory circuits to provide a received signal.
Claim 3
Dependent Claim
61 words
Apparatus as claimed in claim 1, wherein said control means includes clock means for providing clock signals to control the sampling and storing of the associated filter output in the addressed sampling and memory circuit and the read out of the associated stored filter output from the addressed sampling and memory circuit at synchronized times in the plurality of reception channels.
Claim 4
Dependent Claim
33 words
Apparatus as claimed in claim 1, wherein said control means includes means for providing to each mixer a reference signal having a time-dependent phase relationship with respect to the associated transducer element signal.
Claim 5
Dependent Claim
285 words
Apparatus for processing signals, said apparatus comprising: a plurality of groups of reception channels, each group of reception channels including a plurality of reception channels, each reception channel including a mixer for mixing a respective input signal with a time-controlled reference signal, a filter for filtering the mixed signals to produce a low frequency output, and a sampling and memory circuit for periodically sampling the filter output and storing the sampled filter output and for periodically reading out the stored filter output, each group of reception channels further including adding means for adding the read outputs from the plurality of sampling and memory circuits of respective channels to provide a group output, and a group memory for storing the group output; control means for providing write addresses and read addresses for the plurality of sampling and memory circuits and the group memory of each of the plurality of groups of reception channels to cause an addressed sampling and memory circuit to sample and store the associated filter output and to read out the associated stored filter output, with a uniquely selected channel delay time between storing and reading out by that sampling and memory circuit, and to cause respective ones of the group memories to store the associated group output and to read out the associated stored group output with a uniquely selected group delay time between storing and reading out by that group memory, said control means further providing reference signals to the plurality of mixers, the reference signal for a respective mixer being dependent upon the selected channel delay time for that mixer; and further adding means for adding the read outputs from the plurality of group memories to provide a received signal.
Claim 6
Dependent Claim
285 words
Apparatus for processing signals, said apparatus comprising: a plurality of groups of reception channels, each group of reception channels including a plurality of reception channels, each reception channel including a mixer for mixing a respective input signal with a time-controlled reference signal, a filter for filtering the mixed signals to produce a low frequency output, and a sampling and memory circuit for periodically sampling the filter output and storing the sampled filter output and for periodically reading out the stored filter output, each group of reception channels further including adding means for adding the read outputs from the plurality of sampling and memory circuits of respective channels to provide a group output, and a group memory for storing the group output; control means for providing write addresses and read addresses for the plurality of sampling and memory circuits and the group memory of each of the plurality of groups of reception channels to cause an addressed sampling and memory circuit to sample and store the associated filter output and to read out the associated stored filter output, with a uniquely selected channel delay time between storing and reading out by that sampling and memory circuit, and to cause respective ones of the group memories to store the associated group output and to read out the associated stored group output with a uniquely selected group delay time between storing and reading out by that group memory, said control means further providing reference signals to the plurality of mixers, the reference signal for a respective mixer being dependent upon the selected channel delay time for that mixer; and further adding means for adding the read outputs from the plurality of group memories to provide a received signal.
Claim 7
Dependent Claim
27 words
Apparatus as claimed in claim 4, wherein said further adding means comprises a plurality of adders for cascading the read outputs from the plurality of group memories.
Claim 8
Dependent Claim
29 words
Apparatus as claimed in claim 4, wherein said further adding means comprises a plurality of adders for adding the read outputs from the plurality of group memories in parallel.
Claim 9
Dependent Claim
33 words
Apparatus as claimed in claim 6, wherein said control means includes means for providing to each mixer a reference signal having a time-dependent phase relationship with respect to the associated transducer element signal.
Claim 10
Dependent Claim
33 words
Apparatus as claimed in claim 4, wherein said control means includes means for providing to each mixer a reference signal having a time-dependent phase relationship with respect to the associated transducer element signal.
Claim 11
Dependent Claim
93 words
Apparatus as claimed in claim 4, wherein the control means includes clock means for providing clock signals to control the sampling and storing of the associated filter output in the addressed sampling and memory circuit and the read out of the associated stored filter output from the addressed sampling and memory circuit at synchronized times in the plurality of groups and to control the storing of the associated group output in the addressed group memory and the read out of the associated stored group output from the addressed group memory at synchronized times.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-15 | 1997-05-17 | 1997-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-15 | 2001-05-17 | 2001-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-15 | 2005-05-17 | 2005-11-16 | $7700.00 | Window Closed / Lapsed |