Graphics microcomputer for generating geometric figures

Claim 2

A graphics microcomputer having a central processing unit, comprising: an Nth-order polynomial computing circuit which receives constants from said central processing unit to compute consecutively X and Y coordinates of a point on a line segment to be drawn as values of Nth-order polynomials, each pair of X and Y coordinates produced in response to an output clock signal; a first latch circuit in which the value of the X coordinate produced from said Nth-order polynomial computing circuit is latched for one period of the output clock signal before being outputted; a second latch circuit in which the value of the Y coordinate produced from said Nth-order polynomial computing circuit is latched for one period of the output clock signal before being outputted; a direction control circuit which receives the vales of the X and Y coordinates produced from said Nth-order polynomial computing circuit and the outputs of said first and second latch circuits to output a direction of movement in units of dots in accordance with predetermined rules; and an address generating circuit, which receives the direction of movement as an output from said direction control circuit, and computes, in response to each output clock signal, an address of a word containing the dot to be written.

Claim 3

The graphics microcomputer as defined in claim 1 wherein the X and Y coordinates of the point on the line segment are expressed by P.sub.x (t)=A.sub.N *t.sup.N +A.sub.N-1 *t.sup.N-1 +. . . +A.sub.1 *t+A.sub.O ( 1) P.sub.y (t)=B.sub.N *t.sup.N +B.sub.N-1 *t.sup.N-1 +. . . +B.sub.1 *t+B.sub.O ( 2) where A N , A N-1 , . . . B O are constants, t is a parameter that satisfies the condition 0≦t≦1, and N, which is the degree of a curve, is a positive integer.

Claim 4

The graphics microcomputer as defined in claim 1 wherein said Nth-order polynomial computing circuit includes: an X coordinate computing circuit for computing the X coordinate; a Y coordinate computing circuit for computing the Y coordinate; a signal line to be supplied with a new X coordinate; a counter; and a circuit for controlling the coordinate computing circuits, each of said X and Y coordinate computing circuits including a first adder receiving the values of a constant register and a second-order differential register to output the result of addition to said second-order differential register, a second adder receiving the values of said second-order differential register and a first-order differential register to output the result of addition to said first-order differential register, a third adder receiving the values of said first-order differential register and an X coordinate register to output the result of addition to said X coordinate register, and a latch circuit receiving a code bit that is the MSB (most significant bit) of said first-order differential register, said latch circuit holding its value for the cycle period of one output clock signal to output an x direction signal that indicates the direction of movement of a new X coordinate and said X coordinate register outputting the held value to said signal line.