Microcircuit for the implementation of RSA algorithm and ordinary and modular arithmetic, in particular exponentiation, with large operands

Claim 2

Microcircuit means for the implementation of RSA encryption and decryption of an L-bit long message M in a modulo N encryption system having an encryption key E, comprising: a plurality of cell units, wherein each cell unit comprises at least one 1-bit cell and wherein each 1-bit cell comprises: a cyclic right shifting register for storing and shifting a bit of the message M; a first register for storing a bit of inverted modular number N; a left shifting register for storing a bit of a multiplicand B, wherein the left shifting register comprises input means for selectively providing a bit from a group of values comprising 2B and 2B-N; a multiplication register for storing a bit of a multiplication value corresponding to a modulo N multiplication of the message M by the multiplicand; and an addition register for storing a bit of an addition value S, wherein the addition register comprises input means for selectively providing a bit from a group of values comprising S+B and S-N; and adder means, connected to said plurality of 1-bit cell units, for calculating 2B-N, S+B and S-N.

Claim 3

The microcircuit means according to claim 1 wherein the microcircuit further comprises a cyclic left shifting register for storing and shifting the encryption key E.

Claim 4

The microcircuit means according to claim 2 wherein each 1-bit cell further comprises a second register for storing and shifting a bit of the encryption key E.

Claim 5

Microcircuit means according to claim 1, wherein each cell further comprises communication means for performing, within a particular cell, all communication between registers of the particular cell.

Claim 6

Microcircuit means according to claim 1, wherein a first cell unit of said plurality of cell units is connected to both a second unit containing a next lower order bit of M, N, the multiplicand, the multiplication value and the addition value and a third unit containing a next higher order bit of M, N, the multiplicand, the multiplication value and the addition value.

Claim 7

Microcircuit means according to claim 1, wherein each cell unit comprises 4 m 1-bit cells, wherein m is an integer from zero to 4.

Claim 8

Microcircuit means according to claim 1, wherein the adder means comprise at least one adder.

Claim 9

Microcircuit means according to claim 1, wherein the adder means comprise CLA adders.

Claim 10

A circuit for use in a system for calculating the modulo N exponentiation of a number M, the system comprising a cyclic right shifting register M for storing and shifting M, a right shifting register for storing and shifting C, a left shifting register B for storing the multiplicand, a right shifting register S for accumulating modulo N products of two and B and a right shifting register N for storing -N, the circuit comprising: a first register for storing and shifting a bit of M; a second register for storing and shifting a bit of C; a third register for storing a bit of the multiplicand B, wherein the third register has input means for receiving a value corresponding to a modulo N multiplication of said multiplicand by a power of two; a fourth register for storing a bit of -N; and a fifth register for storing a bit from an intermediate value S of the modulo N multiplication, wherein the fifth register comprises input means for selectively providing a bit from a group of values comprising S+B and S-N.

Claim 11

A circuit for use in a system for calculating the modulo N exponentiation of a number M, the system comprising a cyclic right shifting register M for storing and shifting M, a right shifting register for storing and shifting C, a left shifting register B for storing the multiplicand, a right shifting register S for accumulating modulo N products of two and B and a right shifting register N for storing -N, the circuit comprising: a first register for storing and shifting a bit of M; a second register for storing and shifting a bit of C; a third register for storing a bit of the multiplicand B, wherein the third register has input means for receiving a value corresponding to a modulo N multiplication of said multiplicand by a power of two; a fourth register for storing a bit of -N; and a fifth register for storing a bit from an intermediate value S of the modulo N multiplication, wherein the fifth register comprises input means for selectively providing a bit from a group of values comprising S+B and S-N.

Claim 12

The circuit of claim 9 wherein the circuit further comprises adding means for adding the bits from the third and fifth registers and the bits from the fourth and fifth registers in order to generate a new intermediate value of the modulo N multiplication, wherein the adding means comprises carry lookahead means for modifying the additions in response to carry bits received from a lower order circuit.

Claim 13

The circuit of claim 9 wherein the circuit further comprises adding means, connected to the input means of the third register, for computing the value corresponding to the modulo N multiplication of the multiplicand by a power of two, wherein the adding means comprises carry lookahead means for modifying the addition in response to carry bits received from a lower order circuit.

Claim 14

The circuit of claim 9 wherein the circuit further comprises a sixth register for storing and shifting a bit of an encryption-decryption key E.

Claim 15

Apparatus for calculating the product of the modulo N multiplication of a first number by a second number, comprising: a cyclic right shifting register M for storing and shifting the first number; a right shifting register C for storing the product; a right shifting register S for storing intermediate values of the accumulation of powers of the second integer; a left shifting register B for storing the multiplicand; and a right shifting register N for storing a number corresponding to -N, wherein the apparatus is implemented as a plurality of circuits, each circuit comprising: a first storage means for storing and shifting a bit of the first number; a second storage means for storing and shifting a bit of the second number; a third storage means for storing a bit of intermediate values of a multiplicand B corresponding to the second number, wherein the third register has input means for receiving a sum corresponding to a modulo N multiplication of the multiplicand B by a power of two; a fourth storage means for storing a bit of a value corresponding to -N; and a fifth storage means for storing a bit from an intermediate value S of the modulo N multiplication, wherein the fifth storage means comprises input means for selectively providing a bit from a group of values comprising S+B and S-N.

Claim 16

Apparatus for calculating the product of the modulo N multiplication of a first number by a second number, comprising: a cyclic right shifting register M for storing and shifting the first number; a right shifting register C for storing the product; a right shifting register S for storing intermediate values of the accumulation of powers of the second integer; a left shifting register B for storing the multiplicand; and a right shifting register N for storing a number corresponding to -N, wherein the apparatus is implemented as a plurality of circuits, each circuit comprising: a first storage means for storing and shifting a bit of the first number; a second storage means for storing and shifting a bit of the second number; a third storage means for storing a bit of intermediate values of a multiplicand B corresponding to the second number, wherein the third register has input means for receiving a sum corresponding to a modulo N multiplication of the multiplicand B by a power of two; a fourth storage means for storing a bit of a value corresponding to -N; and a fifth storage means for storing a bit from an intermediate value S of the modulo N multiplication, wherein the fifth storage means comprises input means for selectively providing a bit from a group of values comprising S+B and S-N.

Claim 17

The apparatus of claim 13 wherein the circuit further comprises adding means for adding the bits from the third and fifth storage means and the bits from the fourth and fifth storage means in order to generate a new intermediate value of the modulo N multiplication, wherein the adding means comprises carry lookahead means for modifying the additions in response to carry bits received from a lower order circuit.

Claim 18

The apparatus of claim 13 wherein the circuit further comprises adding means, connected to the input means of the third storage means, for computing a sum corresponding to a modulo N multiplication of said multiplicand by a power of two, wherein the adding means comprises carry lookahead means for modifying the addition in response to carry bits received from a lower order circuit.

Claim 19

The apparatus of claim 13 wherein the apparatus further comprises a sixth register for storing and shifting a bit of an encryption/decryption key E and wherein the circuit further comprises sixth storage means for storing and shifting a bit of the encryption/decryption key E.