US5260226A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having different impurity concentration wells
Assignee: Toshiba Corp
•
Filing: 1992-08-12
•
Granted: 1993-11-09
•
Expires: 2012-08-12
Abstract
Abstract A semiconductor device comprises an N-type semiconductor substrate, a first P-type well formed in the semiconductor substrate, a second P-type well formed adjacent to the first P-type well in the semiconductor substrate, the surface impurity concentration of the second P-type well being set lower than that of the first P-type well, a DRAM memory cell structure formed in the first P-type well, and an MOS transistor structure formed in the second P-type well to function in combination with the memory cell structure.
Inventors
- 👤 Shizuo Sawada
- 👤 Syuso Fujii
- 👤 Masaki Ogihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/37; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0156; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
201 words
A method of forming a semiconductor device with a second conductivity type semiconductor substrate comprising the steps of: forming a first well of a first conductivity type with a surface impurity concentration in the semiconductor substrate; forming, separately from the first well, a second well of the first conductivity type with a lower surface impurity concentration than the impurity concentration of the first well; forming, separately from the semiconductor substrate, a third well of the second conductivity type in the second well; forming, separately form the first well and the second well, a fourth well of first conductivity type with a lower impurity concentration than the impurity concentration of the first well and a higher impurity concentration than the impurity concentration of the second well; forming, separately from the first well, the second well, and the fourth well, a fifth well of the second conductivity type in the semiconductor substrate with a higher majority carrier concentration than a majority carrier concentration of the third well; forming a memory cell in the first well; forming a first transistor structure in the second well; forming a second transistor structure in the fourth well; and forming a third transistor structure in the fifth well.
Claim 2
Independent Claim
201 words
A method of forming a semiconductor device with a second conductivity type semiconductor substrate comprising the steps of: forming a first well of a first conductivity type with a surface impurity concentration in the semiconductor substrate; forming, separately from the first well, a second well of the first conductivity type with a lower surface impurity concentration than the impurity concentration of the first well; forming, separately from the semiconductor substrate, a third well of the second conductivity type in the second well; forming, separately form the first well and the second well, a fourth well of first conductivity type with a lower impurity concentration than the impurity concentration of the first well and a higher impurity concentration than the impurity concentration of the second well; forming, separately from the first well, the second well, and the fourth well, a fifth well of the second conductivity type in the semiconductor substrate with a higher majority carrier concentration than a majority carrier concentration of the third well; forming a memory cell in the first well; forming a first transistor structure in the second well; forming a second transistor structure in the fourth well; and forming a third transistor structure in the fifth well.
Claim 3
Dependent Claim
92 words
A method according to claim 1, wherein the steps of forming the first well, the second well, and the fourth well comprise the substeps of: covering the semiconductor substrate with first SiO 2 oxide film; forming a first resist film to have first openings onto a first predetermined portion of the semiconductor substrate; ion-implanting boron into the semiconductor substrate at the first openings of the first resist film; removing the second resist film from the semiconductor substrate; and subjecting the semiconductor substrate to a first heat treatment for a first time period.
Claim 4
Dependent Claim
81 words
A method according to claim 1 or 2, wherein the steps of forming the third well and the fifth well comprise the substeps of: forming a third resist film to have third openings on a third predetermined portion of the semiconductor substrate; ion-implanting phosphorus into the semiconductor substrate at the third openings of the third resist film; removing the third resist film from the semiconductor substrate; and subjecting the semiconductor substrate to a second heat treatment for a second time period.
Claim 5
Dependent Claim
168 words
A method according to claim 1 wherein the method of forming the memory cell in the first well comprises the substeps of: removing the first SiO 2 oxide film from the semiconductor substrate; forming a first field oxide film on the semiconductor substrate; forming a thick resist film on the semiconductor substrate; forming a trench in a predetermined portion of the first well; forming a second SiO 2 oxide film on the first well; etching the trench and etching portions of the second SiO 2 oxide film peripheral to the trench; selectively removing a portion of the thick resist film located around the trench; forming a doped polysilicon layer of said first conductivity type impurity on the semiconductor substrate; subjecting the semiconductor substrate to a third heat treatment for a third period of time; removing the doped polysilicon layer from the semiconductor substrate; forming a third SiO 2 oxide film on the semiconductor substrate; and forming a polysilicon layer around and on the internal surface of the trench.
Claim 6
Dependent Claim
132 words
A method according to claim 1 wherein the steps of forming the first transistor structure, the second transistor structure, and the third transistor structure each comprises the substeps of: forming a fourth SiO 2 oxide film of a predetermined thickness on the semiconductor substrate; forming a second polysilicon layer on the semiconductor substrate; forming first conductivity type diffusion layers at first predetermined positions on the semiconductor substrate; forming second conductivity type diffusion layers at second predetermined positions on the semiconductor substrate; forming a fifth SiO 2 oxide film on the semiconductor substrate; etching predetermined portions of the fifth SiO 2 oxide film; and forming aluminum wiring layers in said etched predetermined portions of the fifth SiO 2 oxide film in respective first conductivity type diffusion layers and second conductivity type diffusion layers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-08 | 1997-05-10 | 1997-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-08 | 2001-05-10 | 2001-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-08 | 2005-05-10 | 2005-11-09 | $7700.00 | Window Closed / Lapsed |