Frequency synthesizer incorporating vernier phase adjuster

Claim 2

A frequency synthesizer including means for previously adjusting the phase of a periodic output signal of frequency F OUT , said synthesizer comprising: source means providing a periodic input signal of frequency F IN ; first divider means responsive to said input signal F IN for producing a signal of frequency F1 where F1=F IN /N; second divider means responsive to said output signal F OUT for producing a signal of frequency F2 where F2=F OUT /M; phase detector means responsive to said signals F1 and F2 for producing a control signal V c ; oscillator means for producing said output signal F OUT as a function of said signal Vd; and phase adjusting means for selectively temporarily simultaneously incrementing the values of M and N to shift the phase of said output signal in one direction or decrementing the values of M and N to shift the phase of said output signal in an opposite direction, while maintaining said output signal frequency F OUT fixed.

Claim 3

The synthesizer of claim 1 wherein said first divider means comprises a first cyclic counter means for counting N cycles of said signal F IN and wherein said phase adjusting means selectively sets N equal to n or n-1 or n+1 during each first counter means cycle; and wherein said second divider means comprises a second cyclic counter means for counting M cycles of said signal F OUT and wherein said phase adjusting means selectively sets M equal to m or m-1 or m+1 during each second counter means cycle.

Claim 4

The synthesizer of claim 2 including controller means for selectively generating a first command or a second command; and wherein said phase adjusting means is responsive to said first command to set M=m-1 and N=n-1 and to said second command to set M=m+1 and N=n+1.

Claim 5

The synthesizer of claim 3 wherein said phase adjusting means is responsive to said first command for presetting said first and second counter means to a first count and responsive to said second command for presetting said first and second counter means to a second count.

Claim 6

The synthesizer of claim 1 wherein N=M+1 or M-1.

Claim 7

The synthesizer of claim 3 wherein said controller means generates a selected command during each counter means cycles to either ADVANCE or RETARD the phase of said output signal.

Claim 8

The synthesizer of claim 3 wherein said controller means repeatedly generates the same command during successive counter means cycles to offset said frequency F OUT in either a first or second direction.

Claim 9

In a phase lock loop frequency synthesizer including controllable oscillator means for providing an output signal of frequency F OUT , phase detector means for producing an oscillator control signal Vc, prescale divide-by-N means responsive to a periodic reference signal of frequency F IN for producing a first phase detector input signal of frequency F1 wherein F1=F IN /N, and feedback divide-by-M means responsive to said output signal for producing a second phase detector input signal of frequency F2 where F2=F OUT /M, an improvement for finely shifting the phase of said output signal in steps equal to 1/F IN- 1/F OUT while maintaining the frequency of said output signal fixed said improvement comprising: phase adjusting means for selectively temporarily simultaneously setting the values of N and M to either (1) n and m, to maintain the phase of said output signal, (2) n-1, and m-1 to advance the phase of said output signal, or (3) n+1 and m+1 to retard the phase of said output signal, respectively.

Claim 10

In a phase lock loop frequency synthesizer including controllable oscillator means for providing an output signal of frequency F OUT , phase detector means for producing an oscillator control signal Vc, prescale divide-by-N means responsive to a periodic reference signal of frequency F IN for producing a first phase detector input signal of frequency F1 wherein F1=F IN /N, and feedback divide-by-M means responsive to said output signal for producing a second phase detector input signal of frequency F2 where F2=F OUT /M, an improvement for finely shifting the phase of said output signal in steps equal to 1/F IN- 1/F OUT while maintaining the frequency of said output signal fixed said improvement comprising: phase adjusting means for selectively temporarily simultaneously setting the values of N and M to either (1) n and m, to maintain the phase of said output signal, (2) n-1, and m-1 to advance the phase of said output signal, or (3) n+1 and m+1 to retard the phase of said output signal, respectively.

Claim 11

The frequency synthesizer of claim 8 wherein said prescale means comprises first counter means for counting N states and said feedback means comprise second counter means for counting M states; means for incrementing said first counter means in response to each cycle of said reference signal; and means for incrementing said second counter means in response to each cycle of said output signal.

Claim 12

The frequency synthesizer of claim 9 wherein said first and second counter means responsively comprise modulo n+1 and modulo m+1 counters; and wherein said phase adjusting means comprises means for selectively presetting said second counter means during each cycle to counts of 0 or 1 or 2.

Claim 13

The synthesizer of claim 10 including shift control means for selectively generating either a first shift command, a no shift command or a second shift command; and wherein said phase adjusting means is responsively responsive to said first shift command for presetting said first and second counter means to said 0 count, to said second shift command for presetting said first and second counter means to said 2 count, and to said no shift command for presetting said first and second counter means to said 1 count.

Claim 14

The synthesizer of claim 8 wherein N=M+1 or M-1 .

Claim 17

The method of claim 13 including the further step of periodically repeating said step of concurrently incrementing or decrementing said values of N and M to offset said frequency F OUT .

Claim 18

The method of claim 13 wherein said step of defining nominal values of N and M includes the step of establishing N=M+1 or M-1.