Symbol timing recovery circuit

Claim 1

A symbol timing recovery circuit for an intermediate frequency M-ary PSK (phase shift keyed) signal, comprising: phase detector means for detecting the instantaneous phase of a received intermediate frequency M-ary PSK signal at successive phase sampling points of each symbol interval of the signal to produce a series of instantaneous phase values, said phase sampling points dividing the symbol interval into equal sections; phase angle detector means for successively detecting a phase angle of each of the equal sections from said instantaneous phase values; phase variation detector means for detecting a difference between the phase angles successively detected by the phase angle detector means during each symbol interval; phase control means for controlling said phase sampling points in accordance with said difference so that same is reduced to zero; and means for determining data sampling points from the controlled phase sampling points, wherein said phase detector means comprises: limiter means for converting said PSK signal into rectangular pulses; an oscillator for generating clock pulses at a multiple of the intermediate frequency; a counter for counting said clock pulses to produce a phase count as said instantaneous phase of the PSK signal; sampler means synchronized with a leading edge of each of said rectangular pulses and each of said phase sampling points for producing a sampling pulse; and a latch connected to the counter and responsive to said sampling pulse for latching the phase count from the counter as said instantaneous phase value.