US5252501A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned single-mask CMOS/BiCMOS twin-well formation with flat surface topography
Assignee: Texas Instruments Inc
•
Filing: 1991-12-30
•
Granted: 1993-10-12
•
Expires: 2011-12-30
Abstract
Abstract A single-mask self-aligned process is disclosed for formation of n and p wells for advanced CMOS and BiCMOS technologies. The proposed process forms n-well and p-well regions using a single microlithography masking step along with a selective semiconductor (Si or GeSi) growth SSG process without producing surface topography or degrading device surface planarity. This simple process ensures uniform and repeatable NMOS and PMOS gate patterning due to flat surface topography. The n-to-p well placement and spacing is self-aligned due to the use of a disposable SSG hard mask.
Inventors
- 👤 Mehrdad M. Moslehi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 01:12
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; H10D84/40; H10D84/401; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
101 words
A single-mask self-aligned process for forming n-wells and p-wells comprising: forming a first dielectric/semiconductor/second dielectric stack over a substrate, said first dielectric being thicker than said second dielectric; etching away a portion of said first dielectric from said stack; implanting a dopant of a selected conductivity type into said substrate using said remaining first dielectric as an implant mask; selectively growing a semiconductor layer using said semiconductor layer as a seed layer; removing the remaining first dielectric; and implanting a dopant of an opposite conductivity type from said selected conductivity type using said selectively grown semiconductor layer as an implantation mask.
Claim 2
Dependent Claim
101 words
A single-mask self-aligned process for forming n-wells and p-wells comprising: forming a first dielectric/semiconductor/second dielectric stack over a substrate, said first dielectric being thicker than said second dielectric; etching away a portion of said first dielectric from said stack; implanting a dopant of a selected conductivity type into said substrate using said remaining first dielectric as an implant mask; selectively growing a semiconductor layer using said semiconductor layer as a seed layer; removing the remaining first dielectric; and implanting a dopant of an opposite conductivity type from said selected conductivity type using said selectively grown semiconductor layer as an implantation mask.
Claim 3
Dependent Claim
21 words
A process as recited in claim 1 wherein said first and second dielectrics comprise oxide and said semiconductor comprises polycrystalline silicon.
Claim 4
Dependent Claim
18 words
A process as recited in claim 2 wherein said first dielectric is etched using an anisotropic oxide etch.
Claim 5
Dependent Claim
16 words
A process as recited in claim 1 wherein said selectively grown layer is one micron thick.
Claim 6
Dependent Claim
26 words
A process as recited in claim 1 wherein a dielectric spacer is formed along said selectively grown layer prior to said implantation of opposite conductivity type.
Claim 7
Dependent Claim
21 words
A process as recited in claim 5 wherein said spacer is selected from the group consisting of oxide, nitride or oxynitride.
Claim 8
Dependent Claim
31 words
A process as recited in claim 1 wherein said substrate is heated after said step of implantation of said opposite conductivity type so as to diffuse said implants into said substrate.
Claim 9
Dependent Claim
15 words
A process as recited in claim 7 wherein said substrate is heated using a furnace.
Claim 10
Dependent Claim
21 words
A process as recited in claim 7 wherein said substrate is heated using rapid thermal processing-based anneal in an ammonia ambient.
Claim 11
Dependent Claim
21 words
A process as recited in claim 7 wherein said semiconductor and first dielectric layers are removed prior to said heating step.
Claim 12
Dependent Claim
91 words
A single-mask self-aligned process for forming n-wells and p-wells comprising: forming a first dielectric/semiconductor/second dielectric stack over a substrate, said first dielectric being thicker than said second dielectric; etching away a portion of said first dielectric from said stack; implanting a dopant of a selected conductivity type into said substrate using said remaining first dielectric as an implant mask; selectively depositing a layer; removing the remaining first dielectric; and implanting a dopant of an opposite conductivity type from said selected conductivity type using said selectively deposited layer as an implantation mask.
Claim 13
Dependent Claim
91 words
A single-mask self-aligned process for forming n-wells and p-wells comprising: forming a first dielectric/semiconductor/second dielectric stack over a substrate, said first dielectric being thicker than said second dielectric; etching away a portion of said first dielectric from said stack; implanting a dopant of a selected conductivity type into said substrate using said remaining first dielectric as an implant mask; selectively depositing a layer; removing the remaining first dielectric; and implanting a dopant of an opposite conductivity type from said selected conductivity type using said selectively deposited layer as an implantation mask.
Claim 14
Dependent Claim
21 words
A process as recited in claim 11 wherein said first and second dielectrics comprise oxide and said semiconductor comprises polycrystalline silicon.
Claim 15
Dependent Claim
18 words
A process as recited in claim 12 wherein said first dielectric is etched using an anisotropic oxide etch.
Claim 16
Dependent Claim
26 words
A process as recited in claim 11 wherein a dielectric spacer is formed along said selectively deposited layer prior to said implantation of opposite conductivity type.
Claim 17
Dependent Claim
21 words
A process as recited in claim 14 wherein said spacer is selected from the group consisting of oxide, nitride or oxynitride.
Claim 18
Dependent Claim
31 words
A process as recited in claim 11 wherein said substrate is heated after said step of implantation of said opposite conductivity type so as to diffuse said implants into said substrate.
Claim 19
Dependent Claim
15 words
A process as recited in claim 16 wherein said substrate is heated using a furnace.
Claim 20
Dependent Claim
21 words
A process as recited in claim 16 wherein said substrate is heated using rapid thermal processing-based anneal in an ammonia ambient.
Claim 21
Dependent Claim
20 words
A process as recited in claim 16 wherein said polycrystalline and first dielectric are removed prior to said heating step.
Claim 22
Dependent Claim
105 words
A single-mask self-aligned process for forming n-wells and p-wells comprising: forming a first dielectric/semiconductor/second dielectric stack over a substrate, said first dielectric being thicker than said second dielectric; etching away a portion of said first dielectric from said stack so as to expose a portion of said semiconductor; implanting a dopant of a selected conductivity type into said substrate using said remaining first dielectric as an implant mask; selectively depositing chemical-vapor deposited tungsten over said exposed semiconductor; removing the remaining first dielectric; and implanting a dopant of an opposite conductivity type from said selected conductivity type using said chemical-vapor deposited tungsten as an implantation mask.
Claim 23
Dependent Claim
105 words
A single-mask self-aligned process for forming n-wells and p-wells comprising: forming a first dielectric/semiconductor/second dielectric stack over a substrate, said first dielectric being thicker than said second dielectric; etching away a portion of said first dielectric from said stack so as to expose a portion of said semiconductor; implanting a dopant of a selected conductivity type into said substrate using said remaining first dielectric as an implant mask; selectively depositing chemical-vapor deposited tungsten over said exposed semiconductor; removing the remaining first dielectric; and implanting a dopant of an opposite conductivity type from said selected conductivity type using said chemical-vapor deposited tungsten as an implantation mask.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-10-11 | 1997-04-12 | 1997-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-10-11 | 2001-04-12 | 2001-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-10-11 | 2005-04-12 | 2005-10-12 | $7700.00 | Window Closed / Lapsed |