US5250832A
Expired / Lapsed
US
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MOS type semiconductor memory device
Assignee: United Microelectronics Corp
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Filing: 1991-10-04
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Granted: 1993-10-05
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Expires: 2011-10-04
Abstract
Abstract A MOS type semiconductor memory device comprises a silicon (Si) substrate of a first conductivity type and a memory cell on a main surface of the Si substrate including a MOS transistor with a first and a second diffused layer highly doped with opposite second conductivity type impurities which provide a source and a drain region spaced apart in the main surface, a gate electrode of a conductive material formed through an insulating layer between the two highly doped diffused layers; an inter-layer insulating film formed to cover the MOS transistor; a capacitor cell formed on the inter-layer film including a lower electrode layer of conductive material formed on the inter-layer insulating film, a portion of which extends through a contact hole formed in the inter-layer insulating layer to penetrate through this layer to reach the junction adjacent to one of the highly doped diffused layers, a dielectric film on the lower electrode layer, and an upper electrode layer formed on the insulating film; and a double-diffused layer doped with the second conductivity type impurities formed to overlap with one of the two highly doped diffused layers at the junction of the Si substrate to make an electric contact between the source-drain circuit of the MOS transistor and the lower electrode.
Inventors
- 👤 Ichiro Murai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:19
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/30; H10B12/31
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
338 words
A MOS type semiconductor memory device comprising: a silicon (Si) substrate of a first conductivity type; and a memory cell formed on a main surface of the Si substrate, the memory cell comprising: a MOS transistor including first and second high concentration diffused layers highly doped with impurities of a second conductivity type different from the first conductivity type and formed in predetermined regions apart from each other in the main surface of the Si substrate so as to provide source and drain of the MOS transistor, and a gate electrode of a conductive material formed on a channel between the first and second high concentration diffused layers with an insulation layer of an insulating material interposed therebetween; an inter-layer insulating film of an insulating material formed so as to cover the MOS transistor; a capacitor cell formed on the inter-layer insulating film and including a lower electrode layer of a conductive material formed on the inter-layer insulating film and having a portion extending through a contact hole formed in the inter-layer insulating film to a junction portion in the Si substrate adjacent to one of the first and second high-concentration diffused layers, a dielectric film formed on the lower electrode layer and an upper electrode layer formed on the dielectric film; and a double-diffused layer doped with impurities of the second conductivity type and formed so as to overlap with one of the first and second high-concentration diffused layers at the junction in the Si substrate so that an electric contact is made between a source-drain circuit of the MOS transistor and the lower electrode, wherein said double-diffused layer comprises a shallow highly doped diffused layer doped with impurities of the second conductivity type and a deep lightly doped diffused layer doped with impurities of the second conductivity type; and wherein said first conductivity type is a P type, and said double-diffused layer includes a high concentration diffused layer highly and shallowly doped with As and a low concentration diffused layer lightly and deeply doped with P.
Claim 2
Dependent Claim
338 words
A MOS type semiconductor memory device comprising: a silicon (Si) substrate of a first conductivity type; and a memory cell formed on a main surface of the Si substrate, the memory cell comprising: a MOS transistor including first and second high concentration diffused layers highly doped with impurities of a second conductivity type different from the first conductivity type and formed in predetermined regions apart from each other in the main surface of the Si substrate so as to provide source and drain of the MOS transistor, and a gate electrode of a conductive material formed on a channel between the first and second high concentration diffused layers with an insulation layer of an insulating material interposed therebetween; an inter-layer insulating film of an insulating material formed so as to cover the MOS transistor; a capacitor cell formed on the inter-layer insulating film and including a lower electrode layer of a conductive material formed on the inter-layer insulating film and having a portion extending through a contact hole formed in the inter-layer insulating film to a junction portion in the Si substrate adjacent to one of the first and second high-concentration diffused layers, a dielectric film formed on the lower electrode layer and an upper electrode layer formed on the dielectric film; and a double-diffused layer doped with impurities of the second conductivity type and formed so as to overlap with one of the first and second high-concentration diffused layers at the junction in the Si substrate so that an electric contact is made between a source-drain circuit of the MOS transistor and the lower electrode, wherein said double-diffused layer comprises a shallow highly doped diffused layer doped with impurities of the second conductivity type and a deep lightly doped diffused layer doped with impurities of the second conductivity type; and wherein said first conductivity type is a P type, and said double-diffused layer includes a high concentration diffused layer highly and shallowly doped with As and a low concentration diffused layer lightly and deeply doped with P.
Claim 3
Dependent Claim
167 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an insulating layer formed on said semiconductor substrate and having a hole reaching said semiconductor substrate; a first impurity-doped region formed at the position opposite to said hole in said semiconductor substrate, said first impurity-doped region containing impurities required to exhibit a second conductivity type different from said first conductivity type of said semiconductor substrate; and a second impurity-doped region which is successive to said first impurity-doped region and formed in said semiconductor substrate at a position further away from said hole than said first impurity-doped region and to at least partly surround said first impurity-doped region, said second impurity-doped region having the same conductivity type as said first impurity-doped region and being doped with the impurities required to exhibit the same conductivity type as said first impurity-doped region but at a lower concentration; and wherein said first impurity-doped region is mainly doped with As and said second impurity-doped region is mainly doped with P.
Claim 4
Dependent Claim
167 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an insulating layer formed on said semiconductor substrate and having a hole reaching said semiconductor substrate; a first impurity-doped region formed at the position opposite to said hole in said semiconductor substrate, said first impurity-doped region containing impurities required to exhibit a second conductivity type different from said first conductivity type of said semiconductor substrate; and a second impurity-doped region which is successive to said first impurity-doped region and formed in said semiconductor substrate at a position further away from said hole than said first impurity-doped region and to at least partly surround said first impurity-doped region, said second impurity-doped region having the same conductivity type as said first impurity-doped region and being doped with the impurities required to exhibit the same conductivity type as said first impurity-doped region but at a lower concentration; and wherein said first impurity-doped region is mainly doped with As and said second impurity-doped region is mainly doped with P.
Claim 5
Dependent Claim
25 words
A semiconductor device according to claim 2, further comprising an electrode electrically connected with said first impurity-doped region at the hole of said insulating layer.
Claim 6
Dependent Claim
25 words
A semiconductor device according to claim 3, further comprising charge storage means for storing charges being in contact with first impurity-doped region through said electrode.
Claim 7
Dependent Claim
41 words
A semiconductor device according to claim 4, further comprising switching means for switching storage and erasure of charges in said charge storage means being in contact with sid charge storage means through said second impurity-doped region and said first impurity-doped region.
Claim 8
Dependent Claim
15 words
A semiconductor device according to claim 5, wherein said switching means comprises a field-effect transistor.
Claim 9
Dependent Claim
236 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an insulating layer formed on said semiconductor substrate and having a hole reaching said semiconductor substrate at a predetermined position; a first impurity-doped region formed at the position opposite to said hole in said semiconductor substrate, said first impurity-doped region containing impurities required to exhibit a second conductivity type different from said first conductivity type of said semiconductor substrate; a second impurity-doped region which is successive to said first impurity-doped region and formed in said semiconductor substrate at a position being further away from said hole than said first impurity-doped region, and to at least partly surround said first impurity-doped region said second impurity-doped region having the same conductivity type as said first impurity-doped region and doped with the impurities required to exhibit the same conductivity type as said first impurity-doped region but at a lower concentration; an electrode formed in the hole of said insulating layer and connected with said first impurity-doped region; charge storage means for storing charges being in contact with said first impurity-doped region through said electrode; switching means for switching storage and erasure of charges in said charge storage means, being in contact with said charge storage means through said second impurity-doped region, and said first impurity-doped region; and wherein said first impurity-doped region is mainly doped with As and said second impurity-doped region is mainly doped with P.
Claim 10
Dependent Claim
236 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; an insulating layer formed on said semiconductor substrate and having a hole reaching said semiconductor substrate at a predetermined position; a first impurity-doped region formed at the position opposite to said hole in said semiconductor substrate, said first impurity-doped region containing impurities required to exhibit a second conductivity type different from said first conductivity type of said semiconductor substrate; a second impurity-doped region which is successive to said first impurity-doped region and formed in said semiconductor substrate at a position being further away from said hole than said first impurity-doped region, and to at least partly surround said first impurity-doped region said second impurity-doped region having the same conductivity type as said first impurity-doped region and doped with the impurities required to exhibit the same conductivity type as said first impurity-doped region but at a lower concentration; an electrode formed in the hole of said insulating layer and connected with said first impurity-doped region; charge storage means for storing charges being in contact with said first impurity-doped region through said electrode; switching means for switching storage and erasure of charges in said charge storage means, being in contact with said charge storage means through said second impurity-doped region, and said first impurity-doped region; and wherein said first impurity-doped region is mainly doped with As and said second impurity-doped region is mainly doped with P.
Claim 11
Dependent Claim
15 words
A semiconductor device according to claim 7, wherein said switching means comprises a field-effect transistor.
Claim 12
Dependent Claim
321 words
A MOS type semiconductor memory device comprising: a silicon (Si) substrate of a first conductivity type; and a memory cell formed on a main surface of the Si substrate, the memory cell comprising: a MOS transistor including first and second high concentration diffused layers highly doped with impurities of a second conductivity type different from the first conductivity type and formed in predetermined regions apart from each other in the main surface of the Si substrate so as to provide source and drain of the MOS transistor, and a gate electrode of a conductive material formed on a channel between the first and second high concentration diffused layers with an insulating layer of an insulating material interposed therebetween; an inter-layer insulating film of an insulating material formed so as to cover the MOS transistor; a capacitor cell formed on the inter-layer insulating film and including a lower electrode layer of a conductive material formed on the inter-layer insulating film and having a portion extending through a contact hole formed in the inter-layer insulating film to a junction portion in the Si substrate adjacent to one of the first and second high-concentration diffused layers, a dielectric film formed on the lower electrode layer and an upper electrode layer formed on the dielectric film; a double-diffused layer doped with impurities of the second conductivity type and formed so as to overlap with one of the first and second high-concentration diffused layers at the junction in the Si substrate so that an electric contact is made between a source-drain circuit of the MOS transistor and the lower electrode, wherein said double-diffused layer comprises a shallow highly doped diffused layer doped with impurities of the second conductivity type and a deep lightly doped diffused layer doped with impurities of the second conductivity type; and wherein said shallow highly doped diffused layer is substantially surrounded by said deep lightly doped diffused layer in said Si substrate.
Claim 13
Dependent Claim
321 words
A MOS type semiconductor memory device comprising: a silicon (Si) substrate of a first conductivity type; and a memory cell formed on a main surface of the Si substrate, the memory cell comprising: a MOS transistor including first and second high concentration diffused layers highly doped with impurities of a second conductivity type different from the first conductivity type and formed in predetermined regions apart from each other in the main surface of the Si substrate so as to provide source and drain of the MOS transistor, and a gate electrode of a conductive material formed on a channel between the first and second high concentration diffused layers with an insulating layer of an insulating material interposed therebetween; an inter-layer insulating film of an insulating material formed so as to cover the MOS transistor; a capacitor cell formed on the inter-layer insulating film and including a lower electrode layer of a conductive material formed on the inter-layer insulating film and having a portion extending through a contact hole formed in the inter-layer insulating film to a junction portion in the Si substrate adjacent to one of the first and second high-concentration diffused layers, a dielectric film formed on the lower electrode layer and an upper electrode layer formed on the dielectric film; a double-diffused layer doped with impurities of the second conductivity type and formed so as to overlap with one of the first and second high-concentration diffused layers at the junction in the Si substrate so that an electric contact is made between a source-drain circuit of the MOS transistor and the lower electrode, wherein said double-diffused layer comprises a shallow highly doped diffused layer doped with impurities of the second conductivity type and a deep lightly doped diffused layer doped with impurities of the second conductivity type; and wherein said shallow highly doped diffused layer is substantially surrounded by said deep lightly doped diffused layer in said Si substrate.
Claim 14
Dependent Claim
26 words
A MOS type semiconductor memory device according to claim 9, wherein said first and second conductivity types are a P type and an N type, respectively.
Claim 15
Dependent Claim
41 words
A MOS type semiconductor memory device according to claim 9, wherein said gate electrode is made of a composite film of a poly Si film doped with impurities of the second conductivity type and a refractory metal silicide film stacked thereon.
References Cited (Backward Citations)
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