Microprocessor having a variable length instruction format

Claim 2

A microprocessor for executing variable length instructions including the basic area including an instruction code and an operand designation area and an extensible area to be added depending on the designation of said basic area to expand said operand designation area, comprising: a basic area decoder means for identifying existence or non-existence of successive basic areas and extensible areas, and for outputting a basic area transition request or extensible area transition request by decoding said basic area; an extensible area decoder means for identifying existence or non-existence of successive extensible areas, and for outputting an extensible area continuation request by decoding said extensible area; and a decode sequencer means for generating a control signal to enable the decoding to said basic area decoder means and extensible area decoder means in accordance with the predetermined sequence, wherein said decode sequence means comprises a first control circuit for generating a control signal for said basic area decoder means responding to said basic area transition request, a second control circuit for generating a control signal for said extensible area decoder means responding to said extensible area transition request or extensible area continuation request, and a third control circuit connected to said first control circuit and said second control circuit to temporarily disable the operations of the first control circuit corresponding to said basic area transition request in case said extensible area transition request or extensible area continuation request is issued.

Claim 3

A microprocessor according to claim 1, further comprising: an instruction bus for supplying instructions; a first input latch circuit connected between said basic area decoder means and said instruction bus; a first output latch circuit for holding an output of said basic area decoder means; and a second output latch circuit connected between said extensible area decoder means and said instruction bus; wherein the input taking operations of said first, second input latch circuits and first, second output latch circuits are controlled by said decoder sequencer means.

Claim 4

A microprocessor according to claim 1, wherein said basic area decoder means comprises an operation code decoder for decoding operation codes, an addressing decoder for decoding addressing modes and a next stage transition request decoder for identifying existence or non-existence of successive basic areas or extensible areas.

Claim 5

A microprocessor according to claim 3, wherein said operation code decoder means comprises a first operation code decoder for decoding the operation code of the first basic area and a second operation code decoder for decoding the operation code of the second basic area.

Claim 6

A microprocessor according to claim 4, wherein said first operation code and second operation code are decoded simultaneously.

Claim 7

A microprocessor according to claim 1, wherein said microprocessor further comprises an instruction register means for taking the data of said instruction under the control of said decoder means.

Claim 8

A microprocessor according to claim 1, wherein said first control circuit comprises a first latch circuit for holding said basic area transition request, a second latch circuit for holding an output of said first latch circuit to output as the basic area decode enable signal and a first gate circuit connected between said first latch circuit and second latch circuit, and said second control circuit comprises a third latch circuit for holding said extensible area transition request, a fourth latch circuit for holding an output of said third latch circuit to output an extensible area decode enable signal and a second gate circuit for receiving an output of said third latch circuit and inhibits transfer of an output of said first latch circuit to said second latch circuit by controlling said first gate circuit in case said extensible area transition request or said extensible area continuation request is issued.

Claim 9

A microprocessor according to claim 2, wherein said decode sequencer means comprises a third gate circuit to inhibit change of condition of said first and second output latch circuits depending on the wait request.

Claim 10

A microprocessor for executing variable length instructions including the basic area including an instruction code and an operand designation area and an extensible area to be added depending on the designation of said basic area to expand said operand designation area, comprising: a basic area decoder means for identifying existence or non-existence of successive basic areas and extensible areas, and for outputting a basic transition request or extensible area transition request by decoding said basic area, said basic area decoder means including an operation code decoder for decoding operation codes, an addressing decoder for decoding addressing modes and a next stage transition request decoder for identifying existence or non-existence of successive basic areas or extensible areas; an extensible area decoder means for identifying existence or non-existence of successive extensible areas, and for outputting an extensible area continuation request by decoding said extensible area; and a decode sequencer means for generating a control signal to enable the decoding to said basic area decoder means and extensible area decoder means in accordance with the predetermined sequence, wherein said decode sequence means comprising a first control circuit for generating a control signal for said basic area decoder means responding to said basic area transition request, a second control circuit for generating a control signal for said extensible area decoder means responding to said extensible area transition request or extensible area continuation request, and a third control circuit connected to said first control circuit and said second control circuit to temporarily disable the operations of the first control circuit corresponding to said basic area transition request in case said extensible area transition request or extensible area continuation request is issued.

Claim 11

A microprocessor for executing variable length instructions including the basic area including an instruction code and an operand designation area and an extensible area to be added depending on the designation of said basic area to expand said operand designation area, comprising: a basic area decoder means for identifying existence or non-existence of successive basic areas and extensible areas, and for outputting a basic transition request or extensible area transition request by decoding said basic area, said basic area decoder means including an operation code decoder for decoding operation codes, an addressing decoder for decoding addressing modes and a next stage transition request decoder for identifying existence or non-existence of successive basic areas or extensible areas; an extensible area decoder means for identifying existence or non-existence of successive extensible areas, and for outputting an extensible area continuation request by decoding said extensible area; and a decode sequencer means for generating a control signal to enable the decoding to said basic area decoder means and extensible area decoder means in accordance with the predetermined sequence, wherein said decode sequence means comprising a first control circuit for generating a control signal for said basic area decoder means responding to said basic area transition request, a second control circuit for generating a control signal for said extensible area decoder means responding to said extensible area transition request or extensible area continuation request, and a third control circuit connected to said first control circuit and said second control circuit to temporarily disable the operations of the first control circuit corresponding to said basic area transition request in case said extensible area transition request or extensible area continuation request is issued.