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US5247401A Expired / Lapsed US ⏱️ 0.0 years remaining

Replay equalization circuit in digital image recorder

Assignee: Hitachi Ltd
•
Filing: 1989-06-12
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Granted: 1993-09-21
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Expires: 2009-06-12
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Abstract

Abstract A replay equalization circuit for reproducing digital image information recorded on a recording medium includes a transducer for reading the digital image information, an equalization circuit connected to the transducer for equalizing an output of the transducer based on a speed information input, a clock recovery circuit connected to the equalization circuit for extracting a clock signal from an output of the equalization circuit for latching the output of the equalization circuit in response to the clock signal.

Inventors

  • 👤 Masuo Umemoto
  • 👤 Hidehiko Sawamura
  • 👤 Yoshizumi Eto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 04:35
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10037; G11B20/10046; G11B5/00; G11B5/02; G11B5/09; H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/931; H04N5/9315; G11B2020/10935; G11B2020/10981

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 260 words
An apparatus for reproducing, at variable replay speeds, digital image information data recorded on a recording medium, comprising: a transducer for reading digital image information data recorded on a recording medium and for producing an output representing a digital image; means for generating a speed information signal representing a variable replay speed of the recording medium; an equalization circuit connected to the transducer for equalizing an output signal of the transducer in response to the speed information signal to produce an equalized output according to the speed information signal; a clock recovery circuit connected to the equalization circuit for extracting a clock signal from the output of the equalization circuit; and a decision circuit connected to the equalization circuit for latching the output of the equalization circuit in response to the clock signal extracted by the clock recovery circuit to produce output data corresponding to the digital image information data recorded on the recording medium; wherein the equalization circuit comprises: a clock signal source circuit for producing a clock signal at different pulse rates according to the received speed information signal; an A/D converter for converting an analog signal from the transducer into a digital signal in response to the clock signal output from the clock supply circuit; a digital filter for compensating the output of the A/D converter in response to the clock signal from the clock signal source circuit; and a D/A converter for converting digital output signals of the digital filter into an analog signal in response to the clock signal from the clock signal source circuit.
Claim 2
Independent Claim 260 words
An apparatus for reproducing, at variable replay speeds, digital image information data recorded on a recording medium, comprising: a transducer for reading digital image information data recorded on a recording medium and for producing an output representing a digital image; means for generating a speed information signal representing a variable replay speed of the recording medium; an equalization circuit connected to the transducer for equalizing an output signal of the transducer in response to the speed information signal to produce an equalized output according to the speed information signal; a clock recovery circuit connected to the equalization circuit for extracting a clock signal from the output of the equalization circuit; and a decision circuit connected to the equalization circuit for latching the output of the equalization circuit in response to the clock signal extracted by the clock recovery circuit to produce output data corresponding to the digital image information data recorded on the recording medium; wherein the equalization circuit comprises: a clock signal source circuit for producing a clock signal at different pulse rates according to the received speed information signal; an A/D converter for converting an analog signal from the transducer into a digital signal in response to the clock signal output from the clock supply circuit; a digital filter for compensating the output of the A/D converter in response to the clock signal from the clock signal source circuit; and a D/A converter for converting digital output signals of the digital filter into an analog signal in response to the clock signal from the clock signal source circuit.
Claim 3
Dependent Claim 129 words
An equalization circuit used in an apparatus which reproduces, through a transducer at variable reply speeds, digital image information data recorded on a recording medium, comprising: a clock signal source circuit for producing a clock signal at different pulse rates indicative of a running speed of the recording medium; an A/D converter for converting an analog signal received from the transducer into a digital signal in response to the clock signal from the clock signal source circuit; a digital filter for compensating the output of the A/D converter in response to the clock signal from the clock signal source circuit; and a D/A converter for converting the digital signal from the digital filter into an analog signal in response to the clock signal from the clock signal source circuit.
Claim 4
Dependent Claim 129 words
An equalization circuit used in an apparatus which reproduces, through a transducer at variable reply speeds, digital image information data recorded on a recording medium, comprising: a clock signal source circuit for producing a clock signal at different pulse rates indicative of a running speed of the recording medium; an A/D converter for converting an analog signal received from the transducer into a digital signal in response to the clock signal from the clock signal source circuit; a digital filter for compensating the output of the A/D converter in response to the clock signal from the clock signal source circuit; and a D/A converter for converting the digital signal from the digital filter into an analog signal in response to the clock signal from the clock signal source circuit.
Claim 5
Independent Claim 423 words
An apparatus for reproducing, at a variable replay speed, digital image information recorded as a sequence of code symbols on a magnetic tape, comprising: means for transporting the magnetic tape at a selectively variable tape speed; a rotating drum contacting the magnetic tape; a magnetic head mounted on the rotating drum and contacting the magnetic tape for reproducing the digital image information recorded on the magnetic tape as a replay signal having a waveform determined by the sequence of code symbols of the digital image information and a tape/head frequency characteristic of the magnetic tape and the magnetic head, the tape/head frequency characteristic varying as the tape speed of the magnetic tape varies; means for detecting the tape speed of the magnetic tape and generating a speed information signal indicative of the detected tape speed; equalization means, receiving the replay signal and the speed information signal and having an equalization characteristic which changes in response to changes in the speed information signal, for equalizing the replay signal in accordance with the equalization characteristic to compensate for the tape/head frequency characteristic, thereby producing an equalized signal substantially free of inter-symbol interference, the equalization means including: means, receiving the speed information signal, for generating a sampling clock signal having a frequency corresponding to the tape speed of the magnetic tape based on the speed information signal, an A/D converter, receiving the replay signal as an input signal and the sampling clock signal as a clock signal, for converting the replay signal into a digital signal, a digital filter, receiving the digital signal as an input signal and the sampling clock signal as a clock signal and having a frequency characteristic which changes in response to changes in the frequency of the sampling clock signal, for filtering the digital signal to compensate for the tape/head frequency characteristic, thereby producing an equalized digital signal substantially free of inter-symbol interference, and a D/A converter, receiving the equalized digital signal as an input signal and the sampling clock signal as a clock signal, for converting the equalized digital signal into an analog signal, the analog signal being the equalized signal; means, receiving the equalized signal, for extracting a clock signal from the equalized signal; and means, receiving the equalized signal and the clock signal, for periodically detecting a level of the equalized signal and converting the detected level into a corresponding one of the code symbols at timings determined by the clock signal, thereby producing an output signal corresponding to the digital image information recorded on the magnetic tape.
Claim 6
Independent Claim 423 words
An apparatus for reproducing, at a variable replay speed, digital image information recorded as a sequence of code symbols on a magnetic tape, comprising: means for transporting the magnetic tape at a selectively variable tape speed; a rotating drum contacting the magnetic tape; a magnetic head mounted on the rotating drum and contacting the magnetic tape for reproducing the digital image information recorded on the magnetic tape as a replay signal having a waveform determined by the sequence of code symbols of the digital image information and a tape/head frequency characteristic of the magnetic tape and the magnetic head, the tape/head frequency characteristic varying as the tape speed of the magnetic tape varies; means for detecting the tape speed of the magnetic tape and generating a speed information signal indicative of the detected tape speed; equalization means, receiving the replay signal and the speed information signal and having an equalization characteristic which changes in response to changes in the speed information signal, for equalizing the replay signal in accordance with the equalization characteristic to compensate for the tape/head frequency characteristic, thereby producing an equalized signal substantially free of inter-symbol interference, the equalization means including: means, receiving the speed information signal, for generating a sampling clock signal having a frequency corresponding to the tape speed of the magnetic tape based on the speed information signal, an A/D converter, receiving the replay signal as an input signal and the sampling clock signal as a clock signal, for converting the replay signal into a digital signal, a digital filter, receiving the digital signal as an input signal and the sampling clock signal as a clock signal and having a frequency characteristic which changes in response to changes in the frequency of the sampling clock signal, for filtering the digital signal to compensate for the tape/head frequency characteristic, thereby producing an equalized digital signal substantially free of inter-symbol interference, and a D/A converter, receiving the equalized digital signal as an input signal and the sampling clock signal as a clock signal, for converting the equalized digital signal into an analog signal, the analog signal being the equalized signal; means, receiving the equalized signal, for extracting a clock signal from the equalized signal; and means, receiving the equalized signal and the clock signal, for periodically detecting a level of the equalized signal and converting the detected level into a corresponding one of the code symbols at timings determined by the clock signal, thereby producing an output signal corresponding to the digital image information recorded on the magnetic tape.

References Cited (Backward Citations)

US4093965A Cited
US4274116A Cited
US4371901A Cited
US4577241A Cited
US4580176A Cited
US4736257A Cited
US4930024A Cited
US5008761A Cited
US5021894A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-09-20 1997-03-22 1997-09-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-09-20 2001-03-22 2001-09-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-09-20 2005-03-22 2005-09-21 $7700.00 Window Closed / Lapsed

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