US5245431A
Expired / Lapsed
US
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Synchronizing signal selection circuit
Assignee: Sharp Corp
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Filing: 1991-08-08
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Granted: 1993-09-14
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Expires: 2011-08-08
Abstract
Abstract In a synchronizing signal selection circuit, in response to the input of a vertical synchronizing signal extracted from a composite synchronizing signal, a control signal is generated. The control signal is in a predetermined state during a period which begins when a first predetermined time period has elapsed after the input of the vertical synchronizing signal, and which terminates when a second predetermined time period has elapsed after the input of the vertical synchronizing signal. The composite synchronizing signal is output when the control signal is in the predetermined state, and a horizontal synchronizing signal separated the composite synchronizing signal is output when the control signal is in a state other than the predetermined state.
Inventors
- 👤 Hisao Okada
- 👤 Shigeyuki Uehira
- 👤 Kuniaki Tanaka
- 👤 Katumi Miki
- 👤 Miki Fukuyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:07
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08; H04N5/10
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
155 words
A synchronizing signal selection circuit comprising: control signal generation means for generating a control signal which is in a predetermined state during a certain period, in response to input of a vertical synchronizing signal extracted from a composite synchronizing signal, said certain period beginning when a first predetermined time period has elapsed after input of said vertical synchronizing signal and terminating when a second predetermined time period has elapsed after input of said vertical synchronizing signal, said composite synchronizing signal being substantially different from a horizontal synchronizing signal separated from said composite synchronizing signal during a period other than said certain period; and selection means, receiving said composite synchronizing signal, said separated horizontal synchronizing signal, and said control signal, for outputting said composite synchronizing signal when said control signal is in said predetermined state and for outputting said separated horizontal synchronizing signal when said control signal is in a state other than said predetermined state.
Claim 2
Dependent Claim
155 words
A synchronizing signal selection circuit comprising: control signal generation means for generating a control signal which is in a predetermined state during a certain period, in response to input of a vertical synchronizing signal extracted from a composite synchronizing signal, said certain period beginning when a first predetermined time period has elapsed after input of said vertical synchronizing signal and terminating when a second predetermined time period has elapsed after input of said vertical synchronizing signal, said composite synchronizing signal being substantially different from a horizontal synchronizing signal separated from said composite synchronizing signal during a period other than said certain period; and selection means, receiving said composite synchronizing signal, said separated horizontal synchronizing signal, and said control signal, for outputting said composite synchronizing signal when said control signal is in said predetermined state and for outputting said separated horizontal synchronizing signal when said control signal is in a state other than said predetermined state.
Claim 3
Dependent Claim
23 words
The synchronizing signal selection circuit according to claim 1, wherein said first predetermined time period is shorter than said second predetermined time period.
Claim 4
Dependent Claim
124 words
The synchronizing signal selection circuit according to claim 1, wherein said control signal generation means comprises: counting means for receiving a periodic pulse string and for counting a number of pulses contained in said periodic pulse string; and decoding means, coupled to an output of said counting means, for setting said control signal to said predetermined state when the output of said counting means becomes a first predetermined value, said first predetermined value corresponding to said first predetermined time period, setting said control signal to the state other than said predetermined state when the output of said counting means becomes a second predetermined value, said second predetermined value corresponding to said second predetermined time period, and outputting said control signal to said selection means.
Claim 5
Dependent Claim
24 words
The synchronizing signal selection circuit according to claim 3, wherein said counting means is reset by a rising edge of said vertical synchronizing signal.
Claim 6
Dependent Claim
111 words
The synchronizing signal selection circuit according to claim 1, wherein said control signal generation means comprises: first pulse signal generation means for generating a first pulse signal in response to input of said vertical synchronizing signal, said first pulse signal ending when said first predetermined time period has elapsed after input of said vertical synchronizing signal; second pulse signal generation means for generating a second pulse signal in response to input of said vertical synchronizing signal, said second pulse signal ending when said second predetermined time period has elapsed after input of said vertical synchronizing signal; and means for generating said control signal based on said first and second pulse signals.
Claim 7
Dependent Claim
113 words
The synchronizing signal selection circuit according to claim 1, wherein said control signal generation means comprises: first pulse signal generation means for generating a first pulse signal in response to input of said vertical synchronizing signal, said first pulse signal ending when said first predetermined time period has elapsed after input of said vertical synchronizing signal; second pulse signal generation means for generating a second pulse signal in response to an end of said first pulse signal, said second pulse signal ending when said second predetermined time period has elapsed after the end of said first pulse signal; and means for generating said control signal based on said first and second pulse signals.
Claim 8
Dependent Claim
38 words
The synchronizing signal selection circuit according to claim 1, further comprising phase-locked loop means, which receives an output of said selection means, for outputting a periodic pulse string as a clock signal to said control signal generation means.
Claim 9
Dependent Claim
99 words
The synchronizing signal selection circuit according to claim 7, wherein said phase-locked loop means comprises: voltage controlled oscillator means for generating said clock signal; frequency divider means, coupled to said voltage controlled oscillator, for dividing said clock signal; phase comparator means, coupled to said selection means and said frequency divider means, for generating a phase comparison signal in accordance with the output of said selection means and said divided clock signal; and low-pass filter means, coupled to said phase comparator means, for filtering said phase comparison signal and outputting said filtered phase comparison signal to said voltage controlled oscillator.
References Cited (Backward Citations)
US4772950A
Cited
US4701796A
Cited
US4709268A
Cited
US4792857A
Cited
US4870297A
Cited
JPH01298875A
Cited
US5132794A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-13 | 1997-03-15 | 1997-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-13 | 2001-03-15 | 2001-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-13 | 2005-03-15 | 2005-09-14 | $7700.00 | Window Closed / Lapsed |