High order switched-capacitor filter with dac input

Claim 2

A digital-to-analog converter, comprising: a digital portion for receiving an n-bit digital word and converting said n-bit digital word to a one-bit digital stream representative of the value of said n-bit digital word; a one bit digital-to-analog converter for receiving the one-bit digital stream and converting it to an analog value, said one-bit digital-to-analog converter including two switched capacitors; and an analog portion for receiving and filtering the output of said one-bit digital-to-analog converter, said analog portion including a switched-capacitor filter having greater than two stages of integration with the noise generated by at least a succeeding stage above order two being influenced by the input stage to said switched-capacitor filter, said one-bit digital-to-analog converter integral with the input stage of said switched capacitor filter.

Claim 3

The digital-to-analog converter of claim 1, wherein said digital portion includes a delta-sigma digital modulator for outputting the one-bit digital stream with a one's density proportional to said digital word.

Claim 4

The digital-to-analog converter of claim 1, wherein siad two switched-capacitors operate from a single reference voltage with one of said switched-capacitors being switched during one logic state of the one-bit data pattern and the other of said switched-capacitors being switched during the other logic state of the one-bit data pattern wherein the charge output by said single reference voltage is substantially independent of the input one-bit data pattern.

Claim 5

A digital-to-analog converter, comprising: a digital portion for receiving an n-bit digital word and converting said n-bit digital word to a one-bit digital stream representative of the value of said n-bit digital word; a one-bit digital-to-analog converter for receiving the one-bit digital stream and converting it to an analog value, said one-bit digital-to-analog converter including two switched-capacitors, said two switched-capacitors operating from a single reference voltage with one of said switched-capacitors being switched during one logic state of the one-bit data pattern and the other of said switched-capacitors being switched during the other logic state of the one-bit data pattern wherein the charge output by said single reference voltage is substantially independent of the input one-bit data pattern; and an analog portion incorporating said one-bit digital-to-analog converter and filtering the output thereof, said analog portion including a switched-capacitor filter having greater than two stages of integration with the noise generated by at least a succeeding stage above order two being influenced by the input stage to siad switched-capacitor filter; wherein the one of said two switched-capacitors not being used has the charge thereon discharged to a charge level substantially similar to the charge level that wold have been present if it were used during a conversion cycle.

Claim 6

A digital-to-analog converter, comprising: a digital portion for receiving an n-bit digital word and converting said n-bit digital word to a one-bit digital stream representative of the value of said n-bit digital word; a one-bit digital-to-analog converter for receiving the one-bit digital stream and converting it to an analog value, said one-bit digital-to-analog converter including two switched-capacitors, said two switched-capacitors operating from a single reference voltage with one of said switched-capacitors being switched during one logic state of the one-bit data pattern and the other of said switched-capacitors being switched during the other logic state of the one-bit data pattern wherein the charge output by said single reference voltage is substantially independent of the input one-bit data pattern; and an analog portion incorporating said one-bit digital-to-analog converter and filtering the output thereof, said analog portion including a switched-capacitor filter having greater than two stages of integration with the noise generated by at least a succeeding stage above order two being influenced by the input stage to siad switched-capacitor filter; wherein the one of said two switched-capacitors not being used has the charge thereon discharged to a charge level substantially similar to the charge level that wold have been present if it were used during a conversion cycle.

Claim 7

A digital-to-analog converter, comprising: a digital portion for receiving an n-bit digital word and converting said n-bit digital word to an m-bit digital stream representative of the value of said n-bit digital word; an m-bit digital-to-analog converter for receiving the m-bit digital stream and converting it to an analog value; and an analog portion for receiving and filtering the output of said m-bit digital-to-analog converter, said analog portion including a switched-capacitor filter having greater than two stages of integration with the noise generated by at least a succeeding stage above order two being influenced by the input stage to said switched-capacitor filter; said switched-capacitor filter including four stages of integration with the output of said fourth stage of integration summed with the input of said first stage such that said first stage reduces the noise (output) generated by said fourth stage of integration.

Claim 8

A digital-to-analog converter, comprising: a digital portion for receiving an n-bit digital word and converting said n-bit digital word to an m-bit digital stream representative of the value of said n-bit digital word; an m-bit digital-to-analog converter for receiving the m-bit digital stream and converting it to an analog value; and an analog portion for receiving and filtering the output of said m-bit digital-to-analog converter, said analog portion including a switched-capacitor filter having greater than two stages of integration with the noise generated by at least a succeeding stage above order two being influenced by the input stage to said switched-capacitor filter; said switched-capacitor filter including four stages of integration with the output of said fourth stage of integration summed with the input of said first stage such that said first stage reduces the noise (output) generated by said fourth stage of integration.

Claim 9

The digital-to-analog converter of claim 5, wherein the output of said fourth stage of integration is summed with each of the succeeding stages to said input stage.

Claim 10

A digital-to-analog converter, comprising: a delta-sigma digital modulator for receiving a digital input value and converting it to a one-bit digital stream having a one's density proportional to siad digital value; a low pass switched-capacitor filter for receiving said one-bit digital stream output by said delta-sigma modulator and converting the one-bit digital stream to an analog value and filtering said analog value to provide a switched-capacitor analog output, said switched-capacitor filter having greater than two stages of integration with the noise of at least a succeeding stage above order two having the noise generated thereby influenced by the input stage to said switched-capacitor filter; said switched-capacitor filter including four stages of integration with the output of said fourth stage summed with the input of said first stage such that siad first stage reduces the noise generated by said fourth stage; and an output low pass filter for converting the output of said switched-capacitor filter to a filtered analog output signal to provide a low impedance output.

Claim 11

A digital-to-analog converter, comprising: a delta-sigma digital modulator for receiving a digital input value and converting it to a one-bit digital stream having a one's density proportional to siad digital value; a low pass switched-capacitor filter for receiving said one-bit digital stream output by said delta-sigma modulator and converting the one-bit digital stream to an analog value and filtering said analog value to provide a switched-capacitor analog output, said switched-capacitor filter having greater than two stages of integration with the noise of at least a succeeding stage above order two having the noise generated thereby influenced by the input stage to said switched-capacitor filter; said switched-capacitor filter including four stages of integration with the output of said fourth stage summed with the input of said first stage such that siad first stage reduces the noise generated by said fourth stage; and an output low pass filter for converting the output of said switched-capacitor filter to a filtered analog output signal to provide a low impedance output.

Claim 12

The digital-to-analog converter of claim 7, wherein the output of said fourth stage is summed with each of the succeeding stages to said input stage.

Claim 13

The digital-to-analog converter of claim 7, wherein the input stage is operable to reduce the noise generated by at least one stage above order two in said switched-capacitor filter.

Claim 14

A digital-to-analog convertor, comprising: a reference voltage; a one-bit digital input for receiving a one-bit input data pattern; a charge/discharge node; and a switching network having two switched-capacitors that are switched to transfer charge from said reference voltage to said charge/discharge node in accordance with a predetermined switching pattern in such a manner as to maintain a substantially constant load on said reference voltage independent of the one-bit data pattern; said switched-capacitors operating from a single reference voltage with one of said switched-capacitors being switched during one logic state of the one-bit data pattern and the other of said switched-capacitors being switched during the other logic state of the one-bit data pattern wherein the charge output by said reference voltage is substantially independent of the one-bit data pattern.

Claim 15

A digital-to-analog convertor, comprising: a reference voltage; a one-bit digital input for receiving a one-bit input data pattern; a charge/discharge node; and a switching network having two switched-capacitors that are switched to transfer charge from said reference voltage to said charge/discharge node in accordance with a predetermined switching pattern in such a manner as to maintain a substantially constant load on said reference voltage independent of the one-bit data pattern; said switched-capacitors operating from a single reference voltage with one of said switched-capacitors being switched during one logic state of the one-bit data pattern and the other of said switched-capacitors being switched during the other logic state of the one-bit data pattern wherein the charge output by said reference voltage is substantially independent of the one-bit data pattern.

Claim 16

The digital-to-analog convertor of claim 10 wherein the one of said two switched-capacitors not being used has the charge thereon being charged to a charge level substantially similar to the charge level that would have been present if it were used during a conversion cycle.

Claim 19

The method of claim 12, wherein the step of converting the m-bit digital stream to an analog value comprises processing the m-bit digital stream through a an m-bit digital-to-analog converter, the digital-to-analog converter being integral with the first stage of the switched-capacitor filter.

Claim 20

The method of claim 12, and further comprising summing the output of the fourth stage of integration with each of the succeeding stages to the input stage of integration.

Claim 21

The method of claim 12, wherein the switched-capacitor filter is a fourth order Butterworth filter.

Claim 22

The method of claim 12, wherein m is equal to one.

Claim 25

The method of claim 17 wherein the step of switching the plurality of the switched-capacitors to transfer charge from the reference voltage comprises: switching one of the two switched-capacitors during one logic of the one-bit data pattern; and switching the other of the switched-capacitors during the other logic state of the one-bit data pattern; wherein the charge supplied by the reference voltage is substantially independent of the one-bit data pattern.