US5244830A
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Method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1992-05-15
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Granted: 1993-09-14
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Expires: 2012-05-15
Abstract
Abstract There is disclosed a method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer, the method comprising the steps: sequentially forming first and second compound semiconductor epitaxial layers on a compound semiconductor wafer; forming a first silicon oxide layer on the second compound semiconductor epitaxial layer at a predetermined low temperature and depositing a poly-crystal silicon layer on the first silicon oxide layer; removing portions of the larminated layers by using a etching technique to form grooves on the compound semiconductor wafer; depositing a second silicon oxide layer overlying thereon at a predetermined low temperature; etching back horizontal portions of the second silicon oxide layer to form side walls in each of the grooves and polishing the polysilicon layer to form a planar surface thereon; bonding the planar surface and the single-crystal silicon wafer by using a thermal process technique; removing the compound semiconductor wafer by using a polishing process technique to expose the first compound semiconductor epitaxial layer; and etching back the first compound semiconductor epitaxial layer and the side walls to form the semiconductor substrate.
Inventors
- 👤 Sang-Won Kang
- 👤 Kyoung-Soo Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:10
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3418; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10P14/3421; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/01; Y; Y10; Y10S; Y10S148/00; Y10S148/149
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
180 words
A method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer comprising the steps of: sequentially forming first and second semiconductor epitaxial layers on a compound semiconductor wafer; forming a first silicon oxide layer on the second compound semiconductor epitaxial layer at a low temperature and depositing a poly-crystal silicon layer on the first silicon oxide layer to form laminated layers; removing portions of the larminated layers by using a etching technique to form grooves on the compound semiconductor wafer; depositing a second silicon oxide layer overlying thereon at a low temperature; etching back horizontal portions of the second silicon oxide layer to form side walls in each of the grooves and polishing the polysilicon layer to form a planar surface thereon; bonding the planar surface and the single-crystal silicon wafer by using a thermal process technique; removing the compound semiconductor wafer by using a polishing process technique to expose the first compound semiconductor epitaxial layer; and etching back the first compound semiconductor epitaxial layer and the side walls to form the semiconductor substrate.
Claim 2
Independent Claim
180 words
A method for manufacturing a semiconductor substrate having a compound semiconductor layer on a single-crystal silicon wafer comprising the steps of: sequentially forming first and second semiconductor epitaxial layers on a compound semiconductor wafer; forming a first silicon oxide layer on the second compound semiconductor epitaxial layer at a low temperature and depositing a poly-crystal silicon layer on the first silicon oxide layer to form laminated layers; removing portions of the larminated layers by using a etching technique to form grooves on the compound semiconductor wafer; depositing a second silicon oxide layer overlying thereon at a low temperature; etching back horizontal portions of the second silicon oxide layer to form side walls in each of the grooves and polishing the polysilicon layer to form a planar surface thereon; bonding the planar surface and the single-crystal silicon wafer by using a thermal process technique; removing the compound semiconductor wafer by using a polishing process technique to expose the first compound semiconductor epitaxial layer; and etching back the first compound semiconductor epitaxial layer and the side walls to form the semiconductor substrate.
Claim 3
Dependent Claim
23 words
The method according to claim 1 wherein the compound semiconductor layer is composed of compound semiconductor epitaxial layers having at least three-storied structure.
Claim 4
Dependent Claim
26 words
The method according to claim 1 wherein concentrations of an impurity injected into the first and second compound semiconductor epitaxial layers are different from each other.
Claim 5
Dependent Claim
28 words
The method according to claim 1 wherein each of the grooves has a mesa structure in which the grooves are arranged in matrix on the compound semiconductor wafer.
Claim 6
Dependent Claim
21 words
The method according to claim 1 wherein the side walls prevent dopant injected into the second semiconductor epitaxial layer from escaping.
Claim 7
Dependent Claim
25 words
The method according to claim 1 wherein the grooves absorb an interface stress caused by a difference in coefficients of thermal expansion between the wafers.
Claim 8
Dependent Claim
24 words
The method according to claim 1 wherein the thermal process for bonding is carried out at a temperature of 100° C. to 1100° C.
Claim 9
Dependent Claim
30 words
The method according to claim 1 wherein thermal process for bonding is carried out firstly at about 300° C. and secondly at a temperature of 100° C. to 1100° C.
Claim 10
Dependent Claim
26 words
The method according to claim 1 wherein an amorphous silicon layer is substituted for a bonding layer to be in contact with the single-crystal silicon wafer.
Claim 11
Dependent Claim
53 words
The method according to claim 1 wherein in the polishing process for removing the compound semiconductor wafer, firstly a mechanical polishing process is carried out to thin the compound semiconductor wafer of a thickness about 30 μm, and secondly a wet etching process is carried out to remove all the remaining semiconductor wafer.
Claim 12
Dependent Claim
20 words
The method according to claim 1 wherein the first compound semiconductor epitaxial layer is removed by a selectively etching process.
Claim 13
Dependent Claim
17 words
The method according to claim 1 wherein the side walls are removed by a wet etching process.
References Cited (Backward Citations)
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JPS6490518A
Cited
US4891329A
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US5064781A
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| 3.5 Years (Year 4) | 1996-09-13 | 1997-03-15 | 1997-09-14 | $2000.00 | Window Closed / Lapsed |
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