US5243490A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ESD protected FAMOS transistor
Assignee: Texas Instruments Inc
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Filing: 1992-09-24
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Granted: 1993-09-07
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Expires: 2012-09-24
Abstract
Abstract A FAMOS memory bit (40) is protected from voltage spike caused by an electrostatic discharge or otherwise by an ESD protection circuit (12). Responsive to a voltage spike on V pp , the ESD protection circuit (12) couples the drain of the FAMOS memory bit (40) to V cc or another high capacitance node.
Inventors
- 👤 George S. Ontko
- 👤 David D. Wilmoth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 12:12
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C16/00; G11C16/02; G11C16/06; G11C16/22; G11C16/225
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
115 words
Circuitry for preventing an electrostatic discharge or other voltage spike affecting a programming signal from programming a memory cell, comprising: a voltage node coupled to receive the programming signal and to an input to the memory cell; and switching circuitry for coupling said memory cell input to a high capacitance node responsive to the electrostatic discharge or other voltage spike affecting the programming signal; said switching circuitry comprising a MOS transistor having a gate coupled to the programming signal, a first source/drain coupled to said memory capacitance node and a second source/drain coupled to said memory cell input such that said MOS transistor conducts between said first and second source/drains responsive to an electrostatic discharge.
Claim 2
Dependent Claim
115 words
Circuitry for preventing an electrostatic discharge or other voltage spike affecting a programming signal from programming a memory cell, comprising: a voltage node coupled to receive the programming signal and to an input to the memory cell; and switching circuitry for coupling said memory cell input to a high capacitance node responsive to the electrostatic discharge or other voltage spike affecting the programming signal; said switching circuitry comprising a MOS transistor having a gate coupled to the programming signal, a first source/drain coupled to said memory capacitance node and a second source/drain coupled to said memory cell input such that said MOS transistor conducts between said first and second source/drains responsive to an electrostatic discharge.
Claim 3
Dependent Claim
25 words
The circuitry of claim 1 wherein said switching circuitry further comprises a capacitor coupled between said programming signal and the gate of said MOS transistor.
Claim 4
Dependent Claim
16 words
The circuitry of claim 2 wherein said capacitor comprises a second MOS transistor having connected source/drains.
Claim 5
Dependent Claim
40 words
The circuitry of claim 2 and further comprising discharge circuitry connected to the gate of said MOS transistor such that the voltage at the gate of said MOS transistor is dissipated after the electrostatic discharge or other voltage spike subsides.
Claim 6
Dependent Claim
31 words
The circuitry of claim 1 and further comprising discharge circuitry to decouple said memory cell input from said high capacitance node after said electrostatic discharge or other voltage spike has subsided.
Claim 7
Dependent Claim
13 words
The circuitry of claim 1 wherein said non-volatile memory comprises a FAMOS transistor.
Claim 8
Dependent Claim
18 words
The circuitry of claim 1 wherein said high capacitance node comprises a node coupled to V cc .
Claim 9
Dependent Claim
76 words
A non-volatile memory device having protection from an electrostatic discharge comprising: a FAMOS transistor having a control gate, a floating gate, a source and a drain; circuitry for selectively programming said FAMOS transistor, said circuitry operable to couple a programming signal to said drain; circuitry for selectively reading said FAMOS transistor; a high capacitance node; and switching circuitry for coupling aid drain to a high capacitance node responsive to an electrostatic discharge affecting said programming signal.
Claim 10
Dependent Claim
76 words
A non-volatile memory device having protection from an electrostatic discharge comprising: a FAMOS transistor having a control gate, a floating gate, a source and a drain; circuitry for selectively programming said FAMOS transistor, said circuitry operable to couple a programming signal to said drain; circuitry for selectively reading said FAMOS transistor; a high capacitance node; and switching circuitry for coupling aid drain to a high capacitance node responsive to an electrostatic discharge affecting said programming signal.
Claim 11
Dependent Claim
18 words
The circuitry of claim 8 wherein said high capacitance node comprises a node coupled to V cc .
Claim 12
Dependent Claim
56 words
The circuitry of claim 8 wherein said switching circuitry comprises a MOS transistor having a gate coupled to aid programming signal, a first source/drain coupled to said FAMOS drain and a second source/drain coupled to said high capacitance node such that said MOS transistor conducts between said first and second source/drains responsive to an electrostatic discharge.
Claim 13
Dependent Claim
25 words
The circuitry of claim 10 wherein said switching circuitry further comprises a capacitor coupled between said programming signal and the gate of said MOS transistor.
Claim 14
Dependent Claim
16 words
The circuitry of claim 11, wherein said capacitor comprises a second MOS transistor having connected source/drains.
Claim 15
Dependent Claim
36 words
The circuitry of claim 12 and further comprising discharge circuitry connected to the gate of said MOS transistor such that the voltage at the gate of said MOS transistor is dissipated after the electrostatic discharge subsides.
Claim 16
Dependent Claim
25 words
The circuitry of claim 8 and further comprising discharge circuitry to decouple said drain from said high capacitance node after said electrostatic discharge has subsided.
Claim 17
Independent Claim
45 words
A method of protecting a FAMOS transistor from a voltage spike on a programming signal, comprising the steps of: detecting a voltage spike on said programming signal; and coupling the drain of the FAMOS transistor to a high capacitance node responsive to said voltage spike.
Claim 18
Independent Claim
45 words
A method of protecting a FAMOS transistor from a voltage spike on a programming signal, comprising the steps of: detecting a voltage spike on said programming signal; and coupling the drain of the FAMOS transistor to a high capacitance node responsive to said voltage spike.
Claim 19
Dependent Claim
25 words
The method of claim 15 and further comprising the step of decoupling the drain from the high capacitance node after the voltage spike has subsided.
Claim 20
Dependent Claim
28 words
the method of claim 15 wherein the step of coupling the drain to a high capacitance source comprises the step of coupling the drain to V cc .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-06 | 1997-03-08 | 1997-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-06 | 2001-03-08 | 2001-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-06 | 2005-03-08 | 2005-09-07 | $7700.00 | Window Closed / Lapsed |