US5243209A
Expired / Lapsed
US
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Semiconductor memory device including junction field effect transistor and capacitor and method of manufacturing the same
Assignee: Mitsubishi Electric Corp
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Filing: 1991-11-06
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Granted: 1993-09-07
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Expires: 2011-11-06
Abstract
Abstract A dynamic random access memory includes a memory cell including a junction field effect transistor and a capacitor. A first conductivity-type semiconductor layer is formed on a main surface of a semiconductor substrate. The semiconductor layer includes a columnar part extending from the main surface of the semiconductor substrate and having a top surface and a sidewall surface. The junction field effect transistor is formed in the columnar part, and the capacitor is formed on the top surface of the columnar part. The junction field effect transistor includes a second conductivity-type impurity region and a gate electrode. The second conductivity-type impurity region is formed on the sidewall surface of the columnar part. The gate electrode is formed to surround the sidewall surface of the columnar part to be electrically in contact with the second conductivity-type impurity, region. The capacitor includes a storage node, a dielectric film, and a cell plate electrode. The storage node is formed to be electrically in contact with the top surface of the columnar part. The dielectric film is formed on the storage node. The cell plate electrode is formed on the dielectric film. It is possible to attain higher degree of integration and higher density of the memory cell without causing variation in the characteristics of the transistor included in the memory cell and without decreasing the noise margin of operation of the semiconductor substrate.
Inventors
- 👤 Tatsuya Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D30/831; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/34; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
179 words
A semiconductor memory device comprising a junction field effect transistor and a capacitor, comprising: a semiconductor substrate having a main surface; a semiconductor layer of a first conductivity type material formed on the main surface of said semiconductor substrate and including a columnar part extending from the main surface of said semiconductor substrate and having a top surface and a sidewall surface; said junction field effect transistor formed in said columnar part; and said capacitor formed on the top surface of said columnar part; said junction field effect transistor including: a conductive layer formed on the sidewall surface of said columnar part; and a gate electrode formed to be electrically in contact with said conductive layer; said capacitor including: a first electrode formed to be electrically in contact with the top surface of said columnar part; a dielectric film formed on said first electrode; and a second electrode formed on said dielectric film, wherein said gate electrodes includes an impurity region of a second conductivity-type opposite the first conductivity-type and covering the entire sidewall surface of said columnar part.
Claim 2
Dependent Claim
179 words
A semiconductor memory device comprising a junction field effect transistor and a capacitor, comprising: a semiconductor substrate having a main surface; a semiconductor layer of a first conductivity type material formed on the main surface of said semiconductor substrate and including a columnar part extending from the main surface of said semiconductor substrate and having a top surface and a sidewall surface; said junction field effect transistor formed in said columnar part; and said capacitor formed on the top surface of said columnar part; said junction field effect transistor including: a conductive layer formed on the sidewall surface of said columnar part; and a gate electrode formed to be electrically in contact with said conductive layer; said capacitor including: a first electrode formed to be electrically in contact with the top surface of said columnar part; a dielectric film formed on said first electrode; and a second electrode formed on said dielectric film, wherein said gate electrodes includes an impurity region of a second conductivity-type opposite the first conductivity-type and covering the entire sidewall surface of said columnar part.
Claim 3
Dependent Claim
25 words
The semiconductor memory device according to claim 1, wherein said gate electrode is formed of a polycrystalline silicon layer including impurity of a second conductivity-type.
Claim 4
Dependent Claim
27 words
The semiconductor memory device according to claim 1, wherein said conductive layer includes a second conductivity-type impurity region formed on the sidewall surface of said columnar part.
Claim 5
Dependent Claim
34 words
The semiconductor memory device according to claim 1, wherein said conductive layer includes a metal layer formed to be in contact with the sidewall surface of said columnar part and cover said sidewall surface.
Claim 6
Dependent Claim
27 words
The semiconductor memory device according to claim 1, wherein said first conductivity-type semiconductor layer is electrically isolated by an isolation oxide film formed on said semiconductor substrate.
Claim 7
Dependent Claim
20 words
The semiconductor memory device according to claim 5 further comprising an inversion preventing layer formed beneath said isolation oxide film.
Claim 8
Dependent Claim
32 words
The semiconductor memory device according to claim 1, wherein said first electrode includes a conductive layer formed on the top surface of said columnar part on said gate electrode to be, insulated.
Claim 9
Independent Claim
142 words
A method of manufacturing a semiconductor memory device comprising a junction field effect transistor and a capacitor comprising the steps of: forming on a main surface of a semiconductor substrate a semiconductor layer of a first conductivity-type material and including a columnar part extending from the main surface of said semiconductor substrate and having a top surface and sidewall surface; forming a conductive layer on the sidewall surface of said columnar part; forming a gate electrode to be electrically in contact with said conductive layer; and having an impurity region of a second conductivity-type opposite the first conductivity-type and covering the entire sidewall surface of said columnar part; forming a first electrode to be electrically in contact with the top surface of said columnar part; forming a dielectric film on said first electrode; and forming a second electrode on said dielectric film.
Claim 10
Independent Claim
142 words
A method of manufacturing a semiconductor memory device comprising a junction field effect transistor and a capacitor comprising the steps of: forming on a main surface of a semiconductor substrate a semiconductor layer of a first conductivity-type material and including a columnar part extending from the main surface of said semiconductor substrate and having a top surface and sidewall surface; forming a conductive layer on the sidewall surface of said columnar part; forming a gate electrode to be electrically in contact with said conductive layer; and having an impurity region of a second conductivity-type opposite the first conductivity-type and covering the entire sidewall surface of said columnar part; forming a first electrode to be electrically in contact with the top surface of said columnar part; forming a dielectric film on said first electrode; and forming a second electrode on said dielectric film.
Claim 11
Dependent Claim
58 words
The method of manufacturing a semiconductor memory device according to claim 8, wherein said step of forming a first conductivity-type semiconductor layer includes the steps of: forming a first conductivity-type semiconductor layer on the whole of the main surface of said semiconductor substrate; and forming said columnar part in a convex shape by selectively removing said semiconductor layer.
Claim 12
Dependent Claim
38 words
The method of manufacturing a semiconductor memory device according to claim 8, wherein said step of forming said conductive layer includes the step of forming a second conductivity-type impurity region on the sidewall surface of said columnar part.
Claim 13
Dependent Claim
65 words
The method of manufacturing a semiconductor memory device according to claim 10, wherein said step of forming a second conductivity-type impurity region includes the steps of forming a polycrystalline silicon layer including a second conductivity-type impurity region to cover the sidewall surface of said columnar part; and doping said second conductivity-type impurity from said polycrystalline silicon layer to the sidewall surface of said columnar part.
Claim 14
Dependent Claim
29 words
The method of manufacturing a semiconductor memory device according to claim 11, wherein said step of forming a gate electrode includes the step of forming said polycrystalline silicon layer.
Claim 15
Dependent Claim
63 words
The method of manufacturing a semiconductor memory device according to claim 8, wherein said step of forming a first conductivity-type semiconductor layer comprises the steps of: forming a first conductivity-type semiconductor layer on the whole of the main surface of said semiconductor substrate; and forming isolation oxide films spaced apart from each other on said semiconductor substrate to electrically isolate said semiconductor layer.
Claim 16
Dependent Claim
254 words
A dynamic random access memory comprising a junction field effect transistor and a capacitor, comprising: a semiconductor substrate having a main surface; a plurality of bit lines formed in a semiconductor layer of a first conductivity-type material on the main surface of said semiconductor or substrate, electrically isolated from each other, and extending in a first direction; a plurality of word lines formed on said bit lines and extending in a second direction crossing said first direction; and a plurality of memory cells arranged at the crossings of said word lines and said bit lines; said bit lines including columnar parts extending from the main surface of said semiconductor substrate at said crossings and each having a top surface and a sidewall surface; each of said memory cells including said capacitor formed on the top surface of said columnar part and said junction field effect transistor formed in said columnar part; said junction field effect transistor including: a conductive layer formed on the sidewall surface of said columnar part; and a gate electrode formed to be electrically in contact with said conductive layer and connected to said work line, said gate electrode including an impurity region of a second conductivity type material opposite the first conductivity-type material and covering the entire sidewall surface of said columnar part; said capacitor including: a first electrode formed to be electrically in contact with the top surface of said columnar part; a dielectric film formed on said first electrode; and a second electrode formed on said dielectric film.
Claim 17
Dependent Claim
254 words
A dynamic random access memory comprising a junction field effect transistor and a capacitor, comprising: a semiconductor substrate having a main surface; a plurality of bit lines formed in a semiconductor layer of a first conductivity-type material on the main surface of said semiconductor or substrate, electrically isolated from each other, and extending in a first direction; a plurality of word lines formed on said bit lines and extending in a second direction crossing said first direction; and a plurality of memory cells arranged at the crossings of said word lines and said bit lines; said bit lines including columnar parts extending from the main surface of said semiconductor substrate at said crossings and each having a top surface and a sidewall surface; each of said memory cells including said capacitor formed on the top surface of said columnar part and said junction field effect transistor formed in said columnar part; said junction field effect transistor including: a conductive layer formed on the sidewall surface of said columnar part; and a gate electrode formed to be electrically in contact with said conductive layer and connected to said work line, said gate electrode including an impurity region of a second conductivity type material opposite the first conductivity-type material and covering the entire sidewall surface of said columnar part; said capacitor including: a first electrode formed to be electrically in contact with the top surface of said columnar part; a dielectric film formed on said first electrode; and a second electrode formed on said dielectric film.
References Cited (Backward Citations)
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