Method of manufacturing a semiconductor memory device having reduced parasitically doped layers

Claim 1

A method of manufacturing a semiconductor memory, comprising the steps of: (a) forming a first dielectric as a gate dielectric on a major surface of a semiconductor substrate of a first conductivity type; (b) forming a plurality of gate electrodes on the first dielectric; (c) implanting impurity ions of a second conductivity type into the semiconductor substrate using the gate electrodes as masks to form source drain diffusion layers, thereby forming bits of the semiconductor memory; (d) forming a second dielectric of a prescribed thickness on the first dielectric between the gate electrodes; (e) coating a photoresist over the existing surface, the photoresist having an opening above each bit into which data is to be written; (f) implanting impurity ions of the second conductivity type into the semiconductor substrate using the photoresist as a mask to write data in the bit; wherein step (b) includes a step of forming the gate electrodes so that the ratio of the height of the gate electrodes to the distance between neighboring gate electrodes equals or exceeds 1, and step (d) includes a step of depositing the second dielectric to a thickness 1/2 or more the distance between the neighboring gate electrodes and a step of etching back the second dielectric to leave the prescribed thickness of the second dielectric unetched on the first dielectric between the gate electrodes.

Claim 2

A method of manufacturing a semiconductor memory, comprising the steps of: (a) forming a first dielectric as a gate dielectric on a major surface of a semiconductor substrate of a first conductivity type; (b) forming a plurality of gate electrodes on the first dielectric; (c) implanting impurity ions of a second conductivity type into the semiconductor substrate using the gate electrodes as masks to form source drain diffusion layers, thereby forming bits of the semiconductor memory; (d) forming a second dielectric of a prescribed thickness on the first dielectric between the gate electrodes; (e) coating a photoresist over the existing surface, the photoresist having an opening above each bit into which data is to be written; (f) implanting impurity ions of the second conductivity type into the semiconductor substrate using the photoresist as a mask to write data in the bit; wherein step (b) includes a step of forming the gate electrodes so that the ratio of the height of the gate electrodes to the distance between neighboring gate electrodes equals or exceeds 1, and step (d) includes a step of depositing the second dielectric to a thickness 1/2 or more the distance between the neighboring gate electrodes and a step of etching back the second dielectric to leave the prescribed thickness of the second dielectric unetched on the first dielectric between the gate electrodes.

Claim 7

A method of manufacturing a semiconductor memory device which includes a peripheral circuit region as well as a memory region, comprising the steps of: (a) forming a field layer on a major surface of a semiconductor substrate of a first conductivity type; (b) forming a first dielectric as a gate dielectric; (c) forming gate electrodes on the first dielectric wherein a plurality of the gate electrodes are formed in the memory region and at least one gate electrode is formed in the peripheral circuit region; (d) implanting low-concentration impurity ions of a second conductivity type into the semiconductor substrate using the gate electrodes as masks to form lightly doped source-drain diffusion layers, thereby forming bits of the memory and lightly doped layers of an LDD transistor in the peripheral circuity region; (e) forming a second dielectric of a prescribed thickness of the first dielectric between the gate electrodes in the memory region, and at the same time, forming the second dielectric on the sides of each gate electrode in the peripheral circuity region; (f) implanting high-concentration impurity ions of the second conductivity type into the semiconductor substrate using the gate electrodes and the second dielectrics as masks to form a highly doped source-drain of the second conductivity type of the LDD transistor in the peripheral circuit region; (g) coating a photoresist over the existing surface, this photoresist having an opening above each bit into which data is to be written; and (h) implanting impurity ions of the second conductivity type into the semiconductor substrate using the photoresist as a mask to write data in the bit; wherein step (c) includes a step of forming the gate electrodes so that the ratio of the height of the gate electrodes to the distance between neighboring gate electrodes equals or exceeds 1, and step (e) includes a step of depositing the second dielectric to a thickness 1/2 or more the distance between the neighboring gate electrodes and a step of etching back the second dielectric to leave the prescribed thickness of the second dielectric unetched on the first dielectric between the gate electrodes in the memory region and to leave the second dielectric on the sides of each gate electrode in the peripheral circuit region.

Claim 8

A method of manufacturing a semiconductor memory device which includes a peripheral circuit region as well as a memory region, comprising the steps of: (a) forming a field layer on a major surface of a semiconductor substrate of a first conductivity type; (b) forming a first dielectric as a gate dielectric; (c) forming gate electrodes on the first dielectric wherein a plurality of the gate electrodes are formed in the memory region and at least one gate electrode is formed in the peripheral circuit region; (d) implanting low-concentration impurity ions of a second conductivity type into the semiconductor substrate using the gate electrodes as masks to form lightly doped source-drain diffusion layers, thereby forming bits of the memory and lightly doped layers of an LDD transistor in the peripheral circuity region; (e) forming a second dielectric of a prescribed thickness of the first dielectric between the gate electrodes in the memory region, and at the same time, forming the second dielectric on the sides of each gate electrode in the peripheral circuity region; (f) implanting high-concentration impurity ions of the second conductivity type into the semiconductor substrate using the gate electrodes and the second dielectrics as masks to form a highly doped source-drain of the second conductivity type of the LDD transistor in the peripheral circuit region; (g) coating a photoresist over the existing surface, this photoresist having an opening above each bit into which data is to be written; and (h) implanting impurity ions of the second conductivity type into the semiconductor substrate using the photoresist as a mask to write data in the bit; wherein step (c) includes a step of forming the gate electrodes so that the ratio of the height of the gate electrodes to the distance between neighboring gate electrodes equals or exceeds 1, and step (e) includes a step of depositing the second dielectric to a thickness 1/2 or more the distance between the neighboring gate electrodes and a step of etching back the second dielectric to leave the prescribed thickness of the second dielectric unetched on the first dielectric between the gate electrodes in the memory region and to leave the second dielectric on the sides of each gate electrode in the peripheral circuit region.