US5241647A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of establishing a clock in the I/O card of a personal computer
Assignee: Winbond Electronics Corp
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Filing: 1992-10-22
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Granted: 1993-08-31
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Expires: 2012-10-22
Abstract
Abstract A method of establishing a clock for the UART circuit provided in a standard I/O card or a combined graphic and I/O card is disclosed. The essential step of the method of the invention is to directly impress the clock of the main board of a personal computer into the UART circuit of the I/O card thereby eliminating the need for an independent crystal for the UART circuit. In an alternative embodiment of the method according to the present invention, the clock for the graphic data processing circuit provided in a combined graphic and I/O card is impressed directly to the UART circuit provided in the same card. The method of establishing a clock in the I/O card also includes a step of processing the directly impressed clock, either from the main board of the personal computer or from the graphic data processing circuit, to obtain the desired clock for the UART circuit with a desired frequency.
Inventors
- 👤 James J. Y. Lin
- 👤 Wen-Chin Pun
- 👤 Wei-Hsiung Chuang
- 👤 Yao-Sung Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:49
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
262 words
A method for electrically impressing a clock signal on a UART circuit in an I/O card used in a personal computer which has a main board clock that is operable to generate an output with a frequency of approximately 14.31818 MHz, said method comprising the steps of: impressing the output of said main board clock on said I/O card; dividing the frequency of the output of said main board clock by 31/4 so as to obtain a controlled clock signal with a frequency of approximately 1.8475 MHz, said step of dividing the frequency of the output of said main board clock including steps of: (a) delivering said output of said main board clock to a first input of a first NAND gate and a first input of an OR gate, (b) delaying and then delivering said output of said main board clock to a second input of said first NAND gate and a second input of said OR gate, (c) delivering an output of said first NAND gate and an output of said OR gate to an exclusive OR gate, (d) delivering an output of said exclusive OR gate to a plurality of flip-flops which are connected in series, (e) delivering an output of each of said flip-flops to a latch circuit, and (f) delivering an output from said latch circuit to said exclusive OR gate and said plurality of flip-flops; and inputting said controlled clock signal into said UART circuit in said I/O card; thereby eliminating a use of an independent clock crystal for said UART circuit in said I/O card.
Claim 2
Independent Claim
262 words
A method for electrically impressing a clock signal on a UART circuit in an I/O card used in a personal computer which has a main board clock that is operable to generate an output with a frequency of approximately 14.31818 MHz, said method comprising the steps of: impressing the output of said main board clock on said I/O card; dividing the frequency of the output of said main board clock by 31/4 so as to obtain a controlled clock signal with a frequency of approximately 1.8475 MHz, said step of dividing the frequency of the output of said main board clock including steps of: (a) delivering said output of said main board clock to a first input of a first NAND gate and a first input of an OR gate, (b) delaying and then delivering said output of said main board clock to a second input of said first NAND gate and a second input of said OR gate, (c) delivering an output of said first NAND gate and an output of said OR gate to an exclusive OR gate, (d) delivering an output of said exclusive OR gate to a plurality of flip-flops which are connected in series, (e) delivering an output of each of said flip-flops to a latch circuit, and (f) delivering an output from said latch circuit to said exclusive OR gate and said plurality of flip-flops; and inputting said controlled clock signal into said UART circuit in said I/O card; thereby eliminating a use of an independent clock crystal for said UART circuit in said I/O card.
Claim 3
Dependent Claim
43 words
The method of claim 1, wherein said step of delivering the output of each of said flip-flops to a latch circuit comprises a step of delivering the output of said plurality of flip-flops to a NOR gate electrically communicating with said latch circuit.
Claim 4
Dependent Claim
36 words
The method of claim 1, wherein said step of delaying and then delivering said output of said main board clock includes a step of delaying the output of said main board clock by approximately 17.5 ns.
Claim 5
Dependent Claim
67 words
The method of claim 1, wherein said step of delivering the output of said first NAND gate and the output of said OR gate to the exclusive OR gate further comprises a step of delivering the output of said first NAND gate and the output of said OR gate to a second NAND gate, said second NAND gate being in electrical communication with said exclusive OR gate.
Claim 6
Independent Claim
238 words
A method for electrically impressing a clock signal on a UART circuit in a card used in a personal computer, said card having a clock that is operable to generate an output with a frequency of approximately 16 MHz, said method comprising steps of: dividing the frequency of the output of said clock by 2 6/3 so as to obtain a controlled clock signal with a frequency of approximately 1.8432 MHz, said step of dividing the frequency of the output of said clock including steps of: (a) delivering said output of said clock to a first input of a first NAND gate and a first input of an OR gate, (b) delaying and then delivering said output of said clock to a second input of said first NAND gate and a second input of said OR gate, (c) delivering an output of said first NAND gate and an output of said OR gate to an exclusive OR gate, (d) delivering an output of said exclusive OR gate to a plurality of flip-flops which are connected in series, (e) delivering an output of each of said flip-flops to a latch circuit, and (f) delivering an output from said latch circuit to said exclusive OR gate and said plurality of flip-flops; and inputting said controlled clock signal into said UART circuit in said card; thereby eliminating a use of an independent clock crystal for said UART circuit in said card.
Claim 7
Independent Claim
238 words
A method for electrically impressing a clock signal on a UART circuit in a card used in a personal computer, said card having a clock that is operable to generate an output with a frequency of approximately 16 MHz, said method comprising steps of: dividing the frequency of the output of said clock by 2 6/3 so as to obtain a controlled clock signal with a frequency of approximately 1.8432 MHz, said step of dividing the frequency of the output of said clock including steps of: (a) delivering said output of said clock to a first input of a first NAND gate and a first input of an OR gate, (b) delaying and then delivering said output of said clock to a second input of said first NAND gate and a second input of said OR gate, (c) delivering an output of said first NAND gate and an output of said OR gate to an exclusive OR gate, (d) delivering an output of said exclusive OR gate to a plurality of flip-flops which are connected in series, (e) delivering an output of each of said flip-flops to a latch circuit, and (f) delivering an output from said latch circuit to said exclusive OR gate and said plurality of flip-flops; and inputting said controlled clock signal into said UART circuit in said card; thereby eliminating a use of an independent clock crystal for said UART circuit in said card.
Claim 8
Dependent Claim
43 words
The method of claim 5, wherein said step of delivering the output of each of said flip-flops to said latch circuit comprise a step of delivering the output of said plurality of flip-flops to a NOR gate electrically communicating with said latch circuit.
Claim 9
Dependent Claim
67 words
The method of claim 5, wherein said step of delivering the output of said first NAND gate and the output of said OR gate to the exclusive OR gate further comprises a step of delivering the output of said first NAND gate and the output of said OR gate to a second NAND gate, said second NAND gate being in electrical communication with said exclusive OR gate.
References Cited (Backward Citations)
US4204206A
Cited
US4761735A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-30 | 1997-03-01 | 1997-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-30 | 2001-03-01 | 2001-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-30 | 2005-03-01 | 2005-08-31 | $7700.00 | Window Closed / Lapsed |