US5239636A
Expired / Lapsed
US
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Buffer memory subsystem for peripheral controllers
Assignee: GlobalFoundries Inc
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Filing: 1988-09-09
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Granted: 1993-08-24
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Expires: 2008-09-09
Abstract
Abstract A buffer memory subsystem for a peripheral controller. A CPU is provided for initiating data transfer. A host adapter is also provided. A memory buffer is used to store data temporarily. The peripheral controller is adapted for operating in an environment having at least two data communications buses: a CPU data communications bus connected between the CPU and the peripheral controller, and a buffer data communications bus, isolated from the CPU data communications bus, and connected to the peripheral controller, to the memory buffer and to the host adapter. In this way, a mechanism is provided to allow the CPU to access the memory buffer by means of the peripheral controller.
Inventors
- 👤 Vineet Dujari
- 👤 Nicos Syrimis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:10
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/10; G06F13/12; G06F13/122; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
148 words
A method of allowing a CPU to access data in a memory device by means of a peripheral controlling means having a plurality of registers, the steps comprising: a) programming a CPU pointer with the address of a predetermined memory location; b) programming a pointer control register; c) initiating a peripheral controller access cycle at a predetermined register location; d) initiating an access cycle in said CPU; e) generating a request for a bus arbiter to allow said CPU to use a data bus; f) lengthening said CPU access cycle by negating a READY signal; g) sending said address of a memory location from said CPU to said memory device via said bus when said bus arbiter allows said CPU access cycle to be executed; h) accessing data at said addressed memory location via said bus; and i) terminating said CPU access cycle by asserting said READY signal.
Claim 2
Independent Claim
148 words
A method of allowing a CPU to access data in a memory device by means of a peripheral controlling means having a plurality of registers, the steps comprising: a) programming a CPU pointer with the address of a predetermined memory location; b) programming a pointer control register; c) initiating a peripheral controller access cycle at a predetermined register location; d) initiating an access cycle in said CPU; e) generating a request for a bus arbiter to allow said CPU to use a data bus; f) lengthening said CPU access cycle by negating a READY signal; g) sending said address of a memory location from said CPU to said memory device via said bus when said bus arbiter allows said CPU access cycle to be executed; h) accessing data at said addressed memory location via said bus; and i) terminating said CPU access cycle by asserting said READY signal.
Claim 3
Dependent Claim
19 words
The method in accordance with claim 1 wherein said data access comprises reading data stored in said memory device.
Claim 4
Dependent Claim
18 words
The method in accordance with claim 1 wherein said data access comprises storing data in said memory device.
Claim 5
Dependent Claim
38 words
The method in accordance with claim 1, the steps further comprising: j) incrementing said CPU pointer to point to the next memory location in said memory device; and k) accessing said next memory location by performing steps (c)-(i).
Claim 6
Dependent Claim
19 words
The method in accordance with claim 4 wherein said data access comprises reading data stored in said memory device.
Claim 7
Dependent Claim
18 words
The method in accordance with claim 4 wherein said data access comprises storing data in said memory device.
Claim 8
Independent Claim
205 words
A method of allowing a CPU to access data in a memory device by means of a peripheral controlling means having a plurality of registers, said method comprising the steps of: a) programming a CPU pointer with the address of a predetermined memory location; b) programming a pointer control register; c) initiating a peripheral controller access cycle at a predetermined register location; d) initiating an access cycle in said CPU; e) generating a request for a bus arbiter to allow said CPU to use a data bus; f) lengthening said CPU access cycle by negating a READY signal; g) sending said address of a memory location from said CPU to said memory device via said bus when said bus arbiter allows said CPU access cycle to be executed, wherein said step of sending said address of a memory location to said memory device comprises (i) sending a first set of predetermined bits of said address specified by said CPU pointer, and (ii) sending a second set of predetermined bits of said address specified by said CPU in the current access cycle thereof; h) accessing data at said addressed memory location via said bus; and i) terminating said CPU access cycle by asserting said READY signal.
Claim 9
Independent Claim
205 words
A method of allowing a CPU to access data in a memory device by means of a peripheral controlling means having a plurality of registers, said method comprising the steps of: a) programming a CPU pointer with the address of a predetermined memory location; b) programming a pointer control register; c) initiating a peripheral controller access cycle at a predetermined register location; d) initiating an access cycle in said CPU; e) generating a request for a bus arbiter to allow said CPU to use a data bus; f) lengthening said CPU access cycle by negating a READY signal; g) sending said address of a memory location from said CPU to said memory device via said bus when said bus arbiter allows said CPU access cycle to be executed, wherein said step of sending said address of a memory location to said memory device comprises (i) sending a first set of predetermined bits of said address specified by said CPU pointer, and (ii) sending a second set of predetermined bits of said address specified by said CPU in the current access cycle thereof; h) accessing data at said addressed memory location via said bus; and i) terminating said CPU access cycle by asserting said READY signal.
Claim 10
Dependent Claim
19 words
The method in accordance with claim 7 wherein said data access comprises reading data stored in said memory device.
Claim 11
Dependent Claim
18 words
The method in accordance with claim 7 wherein said data access comprising storing data in said memory device.
Claim 12
Independent Claim
127 words
A method of allowing a CPU to access data in a device register on a buffer bus, the steps comprising: a) initiating a peripheral controller access cycle at a predetermined register location; b) initiating an access cycle in said CPU; c) generating a request for a bus arbiter to allow said CPU to use said buffer bus; d) lengthening said CPU access cycle; e) converting a value on a portion of a CPU address bus to an address of said device register when said bus arbiter allows said CPU access cycle to be executed via said buffer bus; f) accessing data at said device register location via said buffer bus; g) activating a select signal and an access control signal; and h) terminating said CPU access cycle.
Claim 13
Independent Claim
127 words
A method of allowing a CPU to access data in a device register on a buffer bus, the steps comprising: a) initiating a peripheral controller access cycle at a predetermined register location; b) initiating an access cycle in said CPU; c) generating a request for a bus arbiter to allow said CPU to use said buffer bus; d) lengthening said CPU access cycle; e) converting a value on a portion of a CPU address bus to an address of said device register when said bus arbiter allows said CPU access cycle to be executed via said buffer bus; f) accessing data at said device register location via said buffer bus; g) activating a select signal and an access control signal; and h) terminating said CPU access cycle.
Claim 14
Dependent Claim
17 words
The method in accordance with claim 10 wherein host adapter registers are mapped into said device register.
Claim 15
Dependent Claim
20 words
The method in accordance with claim 11 wherein said data access comprises reading data stored in said host adapter registers.
Claim 16
Dependent Claim
19 words
The method in accordance with claim 11 wherein said data access comprises storing data in said host adapter registers.
Claim 17
Dependent Claim
17 words
The method in accordance with claim 10 wherein error processor registers are mapped into said device register.
Claim 18
Dependent Claim
20 words
The method in accordance with claim 14 wherein said data access comprises reading data stored in said error processor registers.
Claim 19
Dependent Claim
19 words
The method in accordance with claim 14 wherein said data access comprises storing data in said error processor registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |