Converter for interconnecting an asynchronous telecommunication network and a synchronous network

Claim 1

A converter for interconnecting a synchronous network in which information is carried by frame structured synchronous multiplexed signals in which each frame is divided into 32 time slots assigned to at least one communication channel and an asynchronous network in which information is carried by packets having a header and a usable part of 32 bytes, characterized in that it comprises a dual port random access memory (SRAM) having a first port and a second port, a first port management circuit (SPM) connected to the first port and to an incoming synchronous multiplex line (ME) carrying an incoming synchronous multiplexed signal, and to an outgoing synchronous multiplex line (MS) carrying an outgoing synchronous multiplexed signal, said incoming and outgoing synchronous multiplexed signals being frame structured multiplexed signals, and a second port management circuit connected to the second port and to an incoming asynchronous multiplex link (LE) and to an outgoing asynchronous multiplex link (LS) each carrying an asynchronous multiplexed signal made up of packets each relating to one channel, in that, in the synchronous network to asynchronous network direction, the first port management circuit (SPM) stores as first data in the dual port memory (SRAM) at least 32 bytes of each channel in a first write mode, the second port management circuit (APM) reading said stored first data from the dual port memory in a first read mode to assemble the stored data into packets and transmitting the packets on the outgoing asynchronous link (LS) and in that, in the asynchronous network to synchronous network direction, the second port management circuit (APM) stores as second data in the dual port memory (SRAM) at least one packet received on the incoming asynchronous link (LE) in a second write mode, the first port management circuit (SPM) reading said stored second data from the dual port memory in a second read mode to transmit frames on the outgoing synchronous multiplex link (MS), wherein a first operating mode each time slot of a frame is assigned to one channel and that in a second operating mode all the time slots of each frame are assigned to the same channel, the operating mode being imposed by an external command (MF) applied to the first port management circuit (SPM) and to the second port management circuit (APM), and wherein in the first operating mode the dual port memory (SRAM) comprises: two packetizer area (Z0.C, Z1.C) each of 32 packetizer blocks (BC0 through BC31) each of 32 bytes, each block containing one byte of each of 32 channels to be assembled into a packet and each packetizer area being alternately written by the first port management circuit (SPM) in said first write mode and read by the second port management circuit (APM) in said first read mode, 32 depacketizer areas (Z0.D through Z31.D) each of four depacketizer blocks (BD0 through BD3) each of 32 bytes, each depacketizer area being assigned to one channel and each block of a depacketizer area containing a packet relating to the channel of said area; a descriptors area (Z.DES) having a descriptor of one type for each depacketizer block to indicate if the block is full or empty, a read pointer area (Z.PTL) having a read pointer of one byte for each depacketizer area to indicate in said second read mode a byte in said depacketizer area, a write pointer area (Z.PTE) having a write pointer of one byte for each depacketizer area to indicate in said second write mode a block of said area or in said second read mode a received packet relating to said depacketizer area, and a semaphore area (ZS) of one byte to indicate which packetizer area (Z0.C; Z1.C) is filled.