Digital equalization of time interleaved analog to digital converters

Claim 2

In an analog-to-digital converter circuit having a plurality of time interleaved analog-to-digital converters for receiving an analog input signal and generating a plurality of digital signals, the improvement comprising equalization means for compensating for individual variations in converter characteristics found amongst the plurality of analog-to-digital converters, said equalization means including: a reference converter being chosen from one of said analog-to-digital converters, each of the remaining plurality of analog-to-digital converters being referenced to said reference converter; means for providing a differential response between said reference converter and each of the remaining converters; and equalization filter means having individual equalization filters coupled to each of said remaining analog-to-digital converters, each filter receiving input signals from each of the plurality of analog-to-digital converters and having filter coefficients which provide compensation for variations in timing and frequency/phase response between said reference converter and each of the remaining converters.

Claim 3

The improvement of claim 1 wherein said equalization means further comprises gain equalization means for compensating for variations in gain between said reference converter and each of the remaining converters.

Claim 4

The improvement of claim 2 wherein said equalization means further comprises offset equalization means for adjusting for variations in converter offsets found between said reference converter and each of the remaining converters.

Claim 5

The improvement of claim 3 wherein said differential responses are transformed to the Z-domain and placed in a matrix of polynomials, said matrix being inverted to generate the coefficients for each of said equalization filters.

Claim 6

The improvement of claim 4 wherein the converter characteristics of offset, gain, timing, and frequency/phase response of the plurality of analog-to-digital converters are measured periodically and new equalization filter coefficients are calculated to thereby provide for compensation for differences in the characteristics found amongst the analog-to-digital converters.

Claim 7

The improvement of claim 5 wherein the gain and offset equalization means both includes summers and multipliers.

Claim 8

The improvement of claim 6 wherein the sampling rate of each analog-to-digital filter is set equal to the sampling rate of the system.

Claim 9

The improvement of claim 1 further comprising a low pass filter for filtering out high frequency signals and only allowing lower frequency analog signals to pass through to the analog-to-digital converters.

Claim 10

In an analog-to-digital converter circuit having a plurality of time interleaved analog-to-digital converters for receiving an analog input signal and generating a plurality of digital signals, the improvement comprising: equalization means for compensating for individual variations in converter characteristics found amongst the plurality of analog-to-digital converters, said equalization means including: a reference converter being chosen from one of said analog-to-digital converters, each of the remaining plurality of analog-to-digital converters being referenced to said reference converter; means for providing a differential response between said reference converter and each of the remaining converters; equalization filter means having individual equalization filters coupled to each of said remaining analog to-digital converters, said filter means receiving input signals from each of the plurality of analog-to-digital converters and having filter coefficients which provide compensation for variations in timing and frequency/phase response between said reference converter and each of the remaining converters; gain equalization means for compensating for variations in gain between said reference converter and each of the remaining converters; and offset equalization means for adjusting for variations in converter offsets found between said reference converter and each of the remaining converters.

Claim 11

In an analog-to-digital converter circuit having a plurality of time interleaved analog-to-digital converters for receiving an analog input signal and generating a plurality of digital signals, the improvement comprising: equalization means for compensating for individual variations in converter characteristics found amongst the plurality of analog-to-digital converters, said equalization means including: a reference converter being chosen from one of said analog-to-digital converters, each of the remaining plurality of analog-to-digital converters being referenced to said reference converter; means for providing a differential response between said reference converter and each of the remaining converters; equalization filter means having individual equalization filters coupled to each of said remaining analog to-digital converters, said filter means receiving input signals from each of the plurality of analog-to-digital converters and having filter coefficients which provide compensation for variations in timing and frequency/phase response between said reference converter and each of the remaining converters; gain equalization means for compensating for variations in gain between said reference converter and each of the remaining converters; and offset equalization means for adjusting for variations in converter offsets found between said reference converter and each of the remaining converters.

Claim 12

The improvement of claim 9 wherein said differential responses are transformed to the Z-domain and placed in a matrix of polynomials, said matrix being inverted to generate the coefficients for each of said equalization filters.

Claim 13

The improvement of claim 10 wherein the converter characteristics of offset, gain, timing, and frequency/phase response of the plurality of analog-to-digital converters are measured periodically and new equalization filter coefficients are calculated to thereby provide for compensation for differences in the characteristics found amongst the analog-to-digital converters.

Claim 14

The improvement of claim 11 wherein the gain and offset equalization means both includes summers and multipliers.

Claim 15

In an analog-to-digital converter circuit having a plurality of time interleaved analog-to-digital converters for receiving an analog input signal and generating a plurality of digital signals, a method for removing converter offsets and relative variations of gain, timing, and frequency/phase response found amongst the plurality of analog-to-digital converters to compensate for differences amongst the plurality of converters, said method comprising; choosing one of said plurality of analog-to-digital converters as a reference; comparing each of the remaining plurality of analog-to-digital converters with said reference converter; subtracting the frequency response and gain of the reference converter from each of the remaining plurality of analog-to-digital converters to obtain differential response of gain, timing, and phase/frequency response; and equalizing said differential responses to thereby compensate for variations amongst the plurality of converters.

Claim 16

In an analog-to-digital converter circuit having a plurality of time interleaved analog-to-digital converters for receiving an analog input signal and generating a plurality of digital signals, a method for removing converter offsets and relative variations of gain, timing, and frequency/phase response found amongst the plurality of analog-to-digital converters to compensate for differences amongst the plurality of converters, said method comprising; choosing one of said plurality of analog-to-digital converters as a reference; comparing each of the remaining plurality of analog-to-digital converters with said reference converter; subtracting the frequency response and gain of the reference converter from each of the remaining plurality of analog-to-digital converters to obtain differential response of gain, timing, and phase/frequency response; and equalizing said differential responses to thereby compensate for variations amongst the plurality of converters.

Claim 17

The method as defined in claim 13, wherein said method of equalizing further comprises: transforming the differential responses of phase/frequency and timing to the z domain; and solving the inverse z transform to generate coefficients for equalization filters.

Claim 18

The method as defined in claim 14, wherein each equalization filter means includes inputs from each of the plurality of analog-to-digital converters.

Claim 19

An analog-to-digital converter circuit for receiving an analog input signal and generating a plurality of digital signals, said circuit comprising: a plurality of time interleaved analog-to-digital converters; one of said analog-to-digital converters being chosen as a reference converter; each of the remaining plurality of analog-to-digital converters being referenced to said reference converter; and equalization means for providing compensation for individual variations of gain, timing, frequency/phase response and converter offsets found amongst the plurality of analog-to-digital converters, said equalization means including equalization filter means coupled to each of said remaining analog-to-digital converters, said filter means receiving input signals from each of the plurality of analog-to-digital converters and having filter coefficients which provides for compensation for said individual converter variations of timing and frequency/phase response.

Claim 20

An analog-to-digital converter circuit for receiving an analog input signal and generating a plurality of digital signals, said circuit comprising: a plurality of time interleaved analog-to-digital converters; one of said analog-to-digital converters being chosen as a reference converter; each of the remaining plurality of analog-to-digital converters being referenced to said reference converter; and equalization means for providing compensation for individual variations of gain, timing, frequency/phase response and converter offsets found amongst the plurality of analog-to-digital converters, said equalization means including equalization filter means coupled to each of said remaining analog-to-digital converters, said filter means receiving input signals from each of the plurality of analog-to-digital converters and having filter coefficients which provides for compensation for said individual converter variations of timing and frequency/phase response.

Claim 21

The converter circuit as defined in claim 16 further comprises means for obtaining differential response between said reference converter and each of the remaining converters, said differential responses being transformed to the Z-domain and placed in a matrix of polynomials, said matrix being inverted to generate said filter coefficients for each of the equalization filters.