Microcomputer

Claim 2

A microcomputer comprising: a volatile memory; a processor operable selectively in an operation mode and a standby mode in accordance with a standby signal; a standby signal generating circuit for supplying the standby signal to said processor in response to a standby condition; an initial reset circuit for supplying an initial reset signal to said processor when a supply voltage becomes lower than an initial reset value; a power supply circuit for reducing the supply voltage in response to the standby signal to a value of voltage higher than a minimum voltage for said volatile memory to hold data in said volatile memory in the standby mode; and a blocking circuit receiving the standby signal and the initial reset signal for preventing supply of the initial reset signal to said processor when the standby signal indicates the standby mode.

Claim 3

A microcomputer as claimed in claim 1, wherein said power supply circuit includes a capacitor for generating backup power to supply the minimum voltage for keeping the data in said register in the standby mode.

Claim 4

A microcomputer as claimed in claim 2, wherein said blocking circuit has an AND gate receiving inputs of the standby signal and the initial reset signal for outputting said initial reset signal when said standby signal received does not indicate the standby mode; and wherein said standby signal generating circuit produces the standby signal in response to receiving power from the power supply circuit and in response to the standby condition.

Claim 5

A microcomputer as claimed in claim 3, wherein said blocking circuit includes an inverter for inverting the standby signal and supplying an inverted standby signal to said AND gate.

Claim 6

A microcomputer as claimed in claim 1, wherein said power supply includes a battery.

Claim 7

A one chip microcomputer having selective standby and operation modes, comprising: a CPU having a reset input and a standby input, and further having a power supply input; a volatile memory having a power supply input; a power supply circuit for providing a power supply output including normal operating voltage to said power supply inputs and providing a standby voltage substantially less than said normal operating voltage to said power supply inputs in response to a standby signal; a standby signal generating circuit responsive to a standby condition for generating the standby signal and outputting the standby signal to said power supply circuit and said standby input of said CPU; said volatile memory means having a minimum voltage for the volatile memory power supply input that is effective to reliably hold data, which minimum voltage is substantially less than the standby voltage; an initial reset circuit responsive to a reset condition, including a voltage provided by said power supply circuit dropping below an initial reset voltage, for producing an initial reset signal; and means for transmitting the initial reset signal from said initial reset circuit to said reset input of said CPU in response to the absence of said standby signal, and for preventing the transmission of the initial reset signal to said reset input of said CPU when the standby signal indicates the standby mode.

Claim 8

A one chip microcomputer having selective standby and operation modes, comprising: a CPU having a reset input and a standby input, and further having a power supply input; a volatile memory having a power supply input; a power supply circuit for providing a power supply output including normal operating voltage to said power supply inputs and providing a standby voltage substantially less than said normal operating voltage to said power supply inputs in response to a standby signal; a standby signal generating circuit responsive to a standby condition for generating the standby signal and outputting the standby signal to said power supply circuit and said standby input of said CPU; said volatile memory means having a minimum voltage for the volatile memory power supply input that is effective to reliably hold data, which minimum voltage is substantially less than the standby voltage; an initial reset circuit responsive to a reset condition, including a voltage provided by said power supply circuit dropping below an initial reset voltage, for producing an initial reset signal; and means for transmitting the initial reset signal from said initial reset circuit to said reset input of said CPU in response to the absence of said standby signal, and for preventing the transmission of the initial reset signal to said reset input of said CPU when the standby signal indicates the standby mode.

Claim 9

The microcomputer as claimed in claim 6, wherein said means includes an AND circuit having inputs receiving the initial reset signal and the standby signal.

Claim 10

The microcomputer as claimed in claim 7, wherein said means further includes an inverter for inverting the standby signal between the standby signal generating circuit and said AND circuit.

Claim 11

The one chip microcomputer of claim 7, further including an external terminal for receiving an external initial reset signal; and an OR circuit having inputs of the external initial reset signal and the initial reset signal from said initial reset circuit and further having an output connected as one of the inputs of said AND circuit.

Claim 12

The one chip microcomputer of claim 9, further including switch means between said OR circuit and said initial reset circuit for selectively supplying or preventing the supplying of the initial reset signal from said initial reset circuit to said OR circuit and thereby ultimately to said AND circuit.

Claim 13

A microcomputer system, including the one chip microcomputer of claim 6, and further including: an input device for providing an input signal to the one chip microcomputer, and wherein said one chip microcomputer has an input terminal connected to said standby signal generating circuit for receiving the input signal from said input device as a standby condition to switch from the standby mode to the operation mode in response to input from the input device.

Claim 14

A microcomputer system, including the one chip microcomputer of claim 6, and further comprising: a battery power supply; wherein said one chip microcomputer has power supply input terminals connected to said battery power supply and providing power to said power supply circuit so that the power supply output by said power supply circuit is reduced in voltage to provide the reset condition when said battery power supply is disconnected from said one chip microcomputer.

Claim 15

A one chip microcomputer according to claim 6, wherein said volatile memory further includes a volatile data storage memory in addition to said register, having a power supply input connected to receive the power supply output from said power supply circuit and having the minimum voltage for holding data.

Claim 16

The one chip microcomputer of claim 6, wherein said volatile memory includes a program counter.

Claim 17

The microcomputer as claimed in claim 14, wherein said means includes an AND circuit having inputs receiving the initial reset signal and the standby signal.

Claim 18

The one chip microcomputer of claim 15, further including an external terminal for receiving an external initial reset signal; and an OR circuit having inputs of the external initial reset signal and the initial reset signal from said initial reset circuit and further having an output connected as one of the inputs of said AND circuit.

Claim 19

The one chip microcomputer of claim 16, further including switch means between said OR circuit and said initial reset circuit for selectively supplying or preventing the supplying of the initial reset signal from said initial reset circuit to said OR circuit and thereby ultimately to said AND circuit.

Claim 20

A microcomputer system, including the one chip microcomputer of claim 17, and further including: an input device for providing an input signal to the one chip microcomputer, and wherein said one chip microcomputer has an input terminal connected to said standby signal generating circuit for receiving the input signal from said input device as a standby condition to switch from the standby mode to the operation mode in response to input from the input device.

Claim 21

A microcomputer system, including the one chip microcomputer of claim 18, and further comprising: a battery power supply; wherein said one chip microcomputer has power supply input terminals connected to said battery power supply and providing power to said power supply circuit so that the power supply output by said power supply circuit is reduced in voltage to provide the reset condition when said battery power supply is disconnected from said one chip microcomputer.