Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority

Claim 1

A load distributing multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) each including a DSP executing encoding according to a program and a DSP peripheral circuit, said DMM's being arranged in parallel to execute encoding under control such that the amounts of computation assigned to said DSP's are equalized with each other, wherein the improvement comprises: common memories including an input frame memory for storing an input image and n memories for storing locally decoded data, feedback data, coded data, etc., said n+1 common memories respectively having independent memory buses which have addresses and data separated from each other; a task control unit controlling load distribution to said DSP's; a task table for sorting information needed for said task control unit to effect load distribution to said DSP's; and a memory bus control table for storing information needed for said task control unit to effect arbitration between said memory buses, said task control unit dividing an image into a plurality of blocks, retrieving said task table to determine an optimal block to be processed and processing task to be executed for each DMM and assigning said DMM's processing tasks substantially equally to execute encoding, said task control unit further arbitrating between common memory access requests from said DSP's and determining an order of priority by referring to said memory bus control table, thereby arbitrating between said memory buses.