In a data processor an SRT divider having a negative divisor sticky detection circuit

Claim 2

In a data processor, an iterative divider unit for performing non-restoring division, said divider unit receiving a first data operand and a second data operand from a storage unit and performing a sequence of iterative divide operations, in response to a plurality of control signals provided by a controller, to compute a quotient result and a final remainder value, said divider unit comprising: first means having a first input for receiving said first data operand, a second input for receiving a partial remainder value generated during said sequence of iterative divide operations, and an output for providing one of a two's complemented value of said first data operand or said final remainder value, said first means computing and storing said two's complemented value of said first data operand, during said sequence of iterative divide operations, and forming said final remainder value upon completion of said sequence of iterative division operations; and negative divisor sticky detection means coupled to said first means, said negative divisor sticky detection means having a first input coupled to each of a predetermined number of bits of said final remainder value, and a second input coupled to each of a predetermined number of bits of said two's complemented value of said first data operand, said negative divisor sticky detection means performing a bit-wise logical exclusive-OR of said two's complemented value of said first data operand with said final remainder value to determine whether said final remainder value is equal in magnitude to said two's complemented value of said first data operand, and having an output for providing a negative sticky signal indicative thereof.

Claim 3

The divider unit of claim 1 further comprising second means coupled to said first means, said second means having a first input for receiving said first data operand, a second input for receiving said second data operand, and an output for providing said partial remainder value generated during said sequence of iterative divide operations, said partial remainder value comprising a partial remainder sum value and a partial remainder carry value.

Claim 4

The divider unit of claim 1 wherein said first means comprises: adder means for computing and storing said two's complemented value of said first data operand, and for adding said partial remainder sum value and said partial remainder carry value, generated during said sequence of iterative divide operations, to form said final remainder value upon completion of said sequence of iterative division operations; and first storage means coupled to said adder means for storing said final remainder value.

Claim 5

The divider unit of claim 3 wherein said negative divisor sticky detection means comprises: second storage means coupled to adder means for storing said two's complemented value of said first data operand computed by said adder means during said sequence of iterative divide operations; logic means coupled to said first storage means and said second storage means for determining whether said two's complemented value of said first data operand is equal in magnitude to said final remainder value, said logic means receiving said two's complemented value of said first data operand, and said final remainder value, and providing an output signal representative of a bit-wise logical exclusive-OR of said two's complemented value of said first data operand with said final remainder value; and sticky logic means having an input coupled to said logic means for receiving said output signal, and an output for providing said negative sticky signal.

Claim 6

In a data processor, an iterative divider unit for performing non-restoring division, said divider unit receiving a first data operand and a second data operand from a storage unit and performing a sequence of iterative divide operations, in response to a plurality of control signals provided by a controller, to compute a quotient result and a final remainder value, said divider unit comprising: first means having a first input for receiving said first data operand, a second input for receiving a partial remainder value comprising a partial remainder sum value and a partial remainder carry value generated during said sequence of iterative divide operations, and an output for providing one of a two's complemented value of said first data operand or said final remainder value, said first means computing and storing said two's complemented value of said first data operand, during said sequence of iterative divide operations, and forming said final remainder value upon completion of said sequence of iterative division operations; and negative divisor sticky detection means coupled to said first means, said negative divisor sticky detection means having a first input coupled to each of a predetermined number of bits of said final remainder value, and a second input coupled to each of a predetermined number of bits of said two's complemented value of said first data operand, said negative divisor sticky detection means determining whether said final remainder value is equal in magnitude to said two's complemented value of said first data operand, and having an output for providing a negative sticky signal indicative thereof, said negative divisor sticky detection means comprising: storage means coupled to said first means for storing a two's complemented value of said first data operand computed by said first means during said sequence of iterative divide operations; logic means coupled to said storage means, said logic means receiving said two's complemented value of said first data operand, and a final remainder value formed upon completion of said sequence of iterative division operations, said logic means determining whether said two's complemented value of said divisor is equal in magnitude to a final remainder value by computing a bit-wise logical exclusive-OR of said two's complemented value of said first data operand with said final remainder value and providing an output signal indicative thereof; and sticky logic means having an input coupled to said logic means for receiving said output signal, and an output for providing said negative sticky signal.

Claim 7

In a data processor, an iterative divider unit for performing non-restoring division, said divider unit receiving a first data operand and a second data operand from a storage unit and performing a sequence of iterative divide operations, in response to a plurality of control signals provided by a controller, to compute a quotient result and a final remainder value, said divider unit comprising: first means having a first input for receiving said first data operand, a second input for receiving a partial remainder value comprising a partial remainder sum value and a partial remainder carry value generated during said sequence of iterative divide operations, and an output for providing one of a two's complemented value of said first data operand or said final remainder value, said first means computing and storing said two's complemented value of said first data operand, during said sequence of iterative divide operations, and forming said final remainder value upon completion of said sequence of iterative division operations; and negative divisor sticky detection means coupled to said first means, said negative divisor sticky detection means having a first input coupled to each of a predetermined number of bits of said final remainder value, and a second input coupled to each of a predetermined number of bits of said two's complemented value of said first data operand, said negative divisor sticky detection means determining whether said final remainder value is equal in magnitude to said two's complemented value of said first data operand, and having an output for providing a negative sticky signal indicative thereof, said negative divisor sticky detection means comprising: storage means coupled to said first means for storing a two's complemented value of said first data operand computed by said first means during said sequence of iterative divide operations; logic means coupled to said storage means, said logic means receiving said two's complemented value of said first data operand, and a final remainder value formed upon completion of said sequence of iterative division operations, said logic means determining whether said two's complemented value of said divisor is equal in magnitude to a final remainder value by computing a bit-wise logical exclusive-OR of said two's complemented value of said first data operand with said final remainder value and providing an output signal indicative thereof; and sticky logic means having an input coupled to said logic means for receiving said output signal, and an output for providing said negative sticky signal.

Claim 8

The divider of claim 5 wherein said first means comprises: adder means for computing and storing said two's complemented value of said first data operand, and for adding said partial remainder sum value and said partial remainder carry value, generated during said sequence of iterative divide operations, to form said final remainder value upon completion of said sequence of iterative division operations; and adder storage means coupled to said adder means for storing said final remainder value.

Claim 9

The divider of claim 5 wherein said sticky logic means comprises: a first transistor having a control electrode for receiving an evaluate signal provided by said controller, a first current electrode connected to a positive power supply terminal, and a second current electrode for providing said negative sticky signal; a second transistor having a control electrode coupled to the output of said logic means, a first current electrode coupled to the second current electrode of said first transistor, and a second current electrode; and a third transistor having a control electrode for receiving said evaluate signal, a first current electrode connected to the second current electrode of the second transistor, and a second current electrode connected to a negative power supply terminal.

Claim 10

In an iterative divider unit for receiving a first data operand and a second data operand from a storage unit and performing a sequence of iterative divide operations, in response to a plurality of control signals provided by a controller, to compute a quotient result and a final remainder value, a circuit for detecting a negative divisor value comprising: storage means for storing a two's complemented value of said first data operand computed during said sequence of iterative divide operations; logic means coupled to said storage means, said logic means having a first input for receiving said two's complemented value of said first data operand, and a second input for receiving said final remainder value formed upon completion of said sequence of iterative division operations, said logic means determining whether said two's complemented value of said first data operand is equal in magnitude to said final remainder value by computing a bit-wise logical exclusive-OR of said two's complemented value of said first data operand with said final remainder value and providing an output signal indicative thereof; and sticky logic means having an input coupled to said logic means for receiving said output signal, and an output for providing a negative sticky signal.

Claim 11

In an iterative divider unit for receiving a first data operand and a second data operand from a storage unit and performing a sequence of iterative divide operations, in response to a plurality of control signals provided by a controller, to compute a quotient result and a final remainder value, a circuit for detecting a negative divisor value comprising: storage means for storing a two's complemented value of said first data operand computed during said sequence of iterative divide operations; logic means coupled to said storage means, said logic means having a first input for receiving said two's complemented value of said first data operand, and a second input for receiving said final remainder value formed upon completion of said sequence of iterative division operations, said logic means determining whether said two's complemented value of said first data operand is equal in magnitude to said final remainder value by computing a bit-wise logical exclusive-OR of said two's complemented value of said first data operand with said final remainder value and providing an output signal indicative thereof; and sticky logic means having an input coupled to said logic means for receiving said output signal, and an output for providing a negative sticky signal.

Claim 12

The circuit of claim 8 wherein said logic means comprises an exclusive-OR gate.

Claim 13

The circuit of claim 8 wherein said sticky logic means comprises: a first transistor having a control electrode for receiving an evaluate signal provided by said controller, a first current electrode connected to a positive power supply terminal, and a second current electrode for providing said negative sticky signal; a second transistor having a control electrode coupled to the output of said logic means, a first current electrode coupled to the second current electrode of said first transistor, and a second current electrode; and a third transistor having a control electrode for receiving said evaluate signal, a first current electrode connected to the second current electrode of the second transistor, and a second current electrode connected to a negative power supply terminal.