Dynamic switching arrangement for error masking in a system for doubling the digital channel

Claim 1

A dynamic switching circuit arrangement for use in a digital information transmission system, having respective channel input terminals BA and BB for reception of respective channel diversity signals, the channel signals conveying the same information but at different time delays and respectively carrying frames TRA and TRB; comprising for each channel a variable delay memory between the channel input terminal and an intermediate terminal BA', BB' respectively, said intermediate terminals being selection terminals of a switch having an output at which an output signal SO is produced, and control means for said variable delay memories for bringing the signals at said intermediate terminals into phase again; and characterized in that said circuit arrangement further comprises error masking means for controlling said switch so that errors in the received channel signals at the input terminals BA, BB are masked in said output signal SO produced at the output of said switch, said error masking means comprising: a multi-gravity level error detector for each channel for detecting various levels of gravity of error of the channel signal; a priority encoder coupled to both of said error detectors for continuously comparing the error gravity levels of both channel signals and producing control signals dependent on such comparisons; and an R-S flip-flop controlled by the control signals produced by the priority encoder to produce an output which controls said switch so that the output signal SO at the output of said switch carries frames which are selected as between the respective channel signals to obtain those which are of better quality.