Pattern classifier for character recognition

Claim 1

A pattern classifier in a character recognition system having m masks, each mask having a (2n+1)×(2n+1) pixel region, where n=1, 2, 3, . . . , said pixel region defining a character region, a background region, and a don't care region, said character region being different for each of said m masks, said pattern classifier comprising: (2n+1)×(2n+1) input buffer amplifiers, each input buffer amplifier corresponding to a respective pixel location of a (2n+1)×(2n+1) pixel region and having an inverted output line, a non-inverted output line, and a buffer input line for inputting the value of a corresponding character pixel of a character pattern; m output buffer amplifiers, each output buffer line having a mask input line, the mask input line defining one of said m masks and forming a synapse connection with each of said inverted and non-inverted output lines; character pattern synapses selectively coupled to form a synapse connection between said inverted output lines of said input buffer amplifiers and said mask input lines of said output buffer amplifiers in accordance with said character regions of said respective masks, each of said character pattern synapses comprising a PMOS transistor having a source electrode coupled to a first power source voltage, a gate electrode coupled to one of said inverted output lines, and a drain electrode coupled to one of said mask input lines; background pattern synapses selectively coupled to form a synapse connection between said non-inverted output lines of said input buffer amplifiers and said mask input lines of said output buffer amplifiers in accordance with said background regions of said masks, each of said background pattern synapses comprising an NMOS transistor having a source electrode coupled to a second power source voltage, a gate electrode coupled to one of said non-inverted output lines, and a drain electrode coupled to one of said input lines; and bias synapses for biasing said input lines such that said output buffer amplifiers output a predetermined logic level when a character pattern fed to the input buffer amplifiers is identical to one of said masks defined by a corresponding mask input line, each of said bias synapses comprising an NMOS transistor having a source electrode coupled to the second power source, and a gate electrode coupled to the first power source, and a drain electrode coupled to a corresponding one of said mask input lines.