US5232865A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating vertically integrated oxygen-implanted polysilicon resistor
Assignee: Micron Technology Inc
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Filing: 1992-07-15
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Granted: 1993-08-03
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Expires: 2012-07-15
Abstract
Abstract A method for fabricating a high value, vertically integrated resistor begins with an integrated circuit having an unpassivated upper surface that includes designated circuit nodes to be placed in series with the vertical resistor. A layer of passivating material such as boro-phospho silicate glass is deposited on the upper surface of the integrated circuit. Polysilicon vias are formed that extend through the passivating layer and form an electrical ohmic contact with each designated circuit node. The polysilicon vias are subsequently ion implanted with oxygen or nitrogen to increase the resistance thereof to the final desired resistance, which can be greater than 100 megohms, and as much as a gigohm or a terohm. Finally, the vertical resistor is contacted with a metal layer formed on the surface of the passivating layer.
Inventors
- 👤 Monte Manning
- 👤 Roger Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:28
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S148/00; Y10S148/136; Y10S438/00; Y10S438/934
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
99 words
A method of forming a vertically integrated resistor in series with a designated circuit node of an integrated circuit, the method comprising the steps of: forming an integrated circuit having an upper surface including the designated circuit node; depositing a layer of passivating material on the upper surface of the integrated circuit; forming a polysilicon via through the passivating layer, the via electrically coupled to the designated circuit node; and forming a stratified layer within the polysilicon via by doping the polysilicon via with at least one of oxygen and nitrogen thereby increasing the resistance of the polysilicon via.
Claim 2
Independent Claim
99 words
A method of forming a vertically integrated resistor in series with a designated circuit node of an integrated circuit, the method comprising the steps of: forming an integrated circuit having an upper surface including the designated circuit node; depositing a layer of passivating material on the upper surface of the integrated circuit; forming a polysilicon via through the passivating layer, the via electrically coupled to the designated circuit node; and forming a stratified layer within the polysilicon via by doping the polysilicon via with at least one of oxygen and nitrogen thereby increasing the resistance of the polysilicon via.
Claim 3
Dependent Claim
76 words
A method of forming a vertically integrated resistor as in claim 1 in which the step of forming a polysilicon via comprises: removing a portion of the passivating layer to expose the designated circuit node; forming a layer of polysilicon on the passivating layer, the polysilicon layer having a first portion covering the designated circuit node and a second portion covering a portion of the passivating layer; and stripping the second portion of the polysilicon layer.
Claim 4
Dependent Claim
35 words
A method of forming a vertically integrated resistor as in claim 1 in which the step of forming a stratified layer is continued until the resistance of the polysilicon via is greater than 100 megohms.
Claim 5
Dependent Claim
34 words
A method of forming a vertically integrated resistor as in claim 1 further comprising the steps of: forming a metal layer on the passivating layer, the metal layer electrically coupled to the polysilicon via.
Claim 6
Independent Claim
83 words
A method of forming an integrated circuit, the method comprising the steps of: forming a circuit on a substrate, the circuit having a designated circuit node; forming a passivating layer on the circuit, the passivating layer having a contact window that exposes the designated circuit node; covering the designated circuit node with a layer of polysilicon; forming a stratified layer within the layer of polysilicon thereby increasing the resistance of the layer of polysilicon to current flow substantially perpendicular to the stratified layer.
Claim 7
Independent Claim
83 words
A method of forming an integrated circuit, the method comprising the steps of: forming a circuit on a substrate, the circuit having a designated circuit node; forming a passivating layer on the circuit, the passivating layer having a contact window that exposes the designated circuit node; covering the designated circuit node with a layer of polysilicon; forming a stratified layer within the layer of polysilicon thereby increasing the resistance of the layer of polysilicon to current flow substantially perpendicular to the stratified layer.
Claim 8
Dependent Claim
12 words
The method of claim 5 wherein the circuit is a memory cell.
Claim 9
Dependent Claim
29 words
The method of claim 5 further comprising the step of: forming a conductive layer on the layer of polysilicon, the conductive layer electrically coupled to the layer of polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-02 | 1997-02-01 | 1997-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-02 | 2001-02-01 | 2001-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-02 | 2005-02-01 | 2005-08-03 | $7700.00 | Window Closed / Lapsed |